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d a t a sh eet preliminary speci?cation supersedes data of 1999 aug 02 file under integrated circuits, ic02 2000 feb 23 integrated circuits saa55xx enhanced tv microcontrollers with on-screen display (osd)
2000 feb 23 2 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx contents 1 features 2 general description 3 quick reference data 4 ordering information 5 block diagram 6 pinning information 6.1 pinning 6.2 pin description 7 microcontroller 7.1 microcontroller features 8 memory organization 8.1 rom bank switching 8.2 security bits - program and verify 8.3 ram organisation 8.4 data memory 8.5 sfr memory 8.6 character set feature bits 8.7 external (auxiliary) memory 9 power-on reset 10 reduced power modes 10.1 idle mode 10.2 power-down mode 10.3 standby mode 11 i/o facility 11.1 i/o ports 11.2 port type 11.3 port alternative functions 11.4 led support 12 interrupt system 12.1 interrupt enable structure 12.2 interrupt enable priority 12.3 interrupt vector address 12.4 level/edge interrupt 13 timer/counter 14 watchdog timer 14.1 watchdog timer operation 15 pulse width modulators 15.1 pwm control 15.2 tuning pulse width modulator (tpwm) 15.3 software adc (sad) 16 i 2 c-bus serial i/o 16.1 i 2 c-bus port selection 17 memory interface 17.1 memory structure 17.2 memory mapping 17.3 addressing memory 17.4 page clearing 18 data capture 18.1 data capture features 19 display 19.1 display features 19.2 display modes 19.3 display feature descriptions 19.4 character and attribute coding 19.5 screen and global controls 19.6 screen colour 19.7 text display controls 19.8 soft scroll action 19.9 display positioning 19.10 character set 19.11 rom addressing 19.12 redefinable characters 19.13 display synchronization 19.14 video/data switch (fast blanking) polarity 19.15 video/data switch adjustment 19.16 rgb brightness control 19.17 contrast reduction 20 memory mapped registers (mmr) 21 limiting values 22 characteristics 23 quality and reliability 23.1 group a 23.2 group b 23.3 group c 24 application information 25 emc guidelines 26 references 27 package outline 28 soldering 28.1 introduction to soldering through-hole mount packages 28.2 soldering by dipping or by solder wave 28.3 manual soldering 28.4 suitability of through-hole mount ic packages for dipping and wave soldering methods 29 definitions 30 life support applications 31 purchase of philips i 2 c components
2000 feb 23 3 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 1 features single-chip microcontroller with integrated osd versions available with integrated data capture otp memory for both program rom and character sets single power supply: 3.0 to 3.6 v 5 v tolerant digital inputs and i/o 29 i/o ports via individual addressable controls programmable i/o for push-pull, open-drain and quasi-bidirectional two port lines with 8 ma sink (at <0.4 v) capability, for direct drive of led single crystal oscillator for microcontroller, osd and data capture power reduction modes: idle, power-down and standby byte level i 2 c-bus interface with dual port i/o 32 dynamically redefinable characters for osds special graphic characters allowing four colours per character selectable character height 9, 10, 13 and 16 tv lines pin compatibility throughout family operating temperature: - 20 to +70 c. 2 general description the saa55xx family of microcontrollers are a derivative of the philips industry-standard 80c51 microcontroller and are intended for use as the central control mechanism in a television receiver. they provide control functions for the television system, on-screen display (osd) and some versions include an integrated data capture and display function. the data capture hardware has the capability of decoding and displaying both 525 and 625-line world system teletext (wst), closed caption (cc) information, video programming information (vps) and wide screen signalling (wss) information. the same display hardware is used both for teletext, closed caption and on-screen display, which means that the display features available give greater flexibility to differentiate the tv set. the saa55xx family offers a range of functionality from non-text, 16-kbyte program rom and 256-byte ram, to a 10 page text version, 128-kbyte program rom and 2.25-kbyte ram. 3 quick reference data symbol parameter min. typ. max. unit supply v ddx any supply voltage (v dd to v ss ) 3.0 3.3 3.6 v i ddp periphery supply current 1 -- ma i ddc core supply current - 15 18 ma i ddc(id) idle mode core supply current - 4.6 6 ma i ddc(pd) power-down mode core supply current - 0.76 1 ma i ddc(stb) standby mode core supply current - 5.1 9 ma i dda analog supply current - 45 48 ma i dda(id) idle mode analog supply current - 0.87 1.0 ma i dda(stb) standby mode analog supply current - 809 950 m a i dda(pd) power-down mode analog supply current - 0.45 0.7 ma f xtal crystal frequency - 12 - mhz t amb ambient temperature - 20 - +70 c t stg storage temperature - 55 - +125 c
2000 feb 23 4 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 4 ordering information notes 1. nnnn is a four digit number uniquely referencing the microcontroller program mask. 2. for details of the lqfp100 package, please contact your local regional sales office for availability. type number (1) package (2) rom ram text pages name description version saa5530ps/nnnn sdip52 plastic shrink dual in-line package; 52 leads (600 mil) sot247-1 16-kbyte 256-byte 1 saa5531ps/nnnn 32-kbyte 512-byte 1 saa5532ps/nnnn 48-kbyte 750-byte 1 saa5533ps/nnnn 64-kbyte 1-kbyte 1 saa5561ps/nnnn 32-kbyte 750-byte 10 saa5562ps/nnnn 48-kbyte 1-kbyte 10 saa5563ps/nnnn 64-kbyte 1.2-kbyte 10 saa5564ps/nnnn 96-kbyte 1.5-kbyte 10 SAA5565PS/nnnn 128-kbyte 2-kbyte 10
2000 feb 23 5 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 5 block diagram fig.1 block diagram (top level architecture). handbook, full pagewidth mbk950 microprocessor (80c51) sram (256-byte) rom (16 to 128-kbyte) memory interface display r g b vds vsync hsync cvbs data capture dram (3 to 12-kbyte) tv control and interface i 2 c-bus, general i/o display timing cvbs data capture timing
2000 feb 23 6 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 6 pinning information 6.1 pinning fig.2 sdip52 pin configuration. handbook, halfpage saa55xx mbk951 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 p2.0/tpwm p2.1/pwm0 p2.2/pwm1 p2.3/pwm2 p2.4/pwm3 p2.5/pwm4 p2.6/pwm5 p2.7/pwm6 p3.0/adc0 p3.1/adc1 p3.2/adc2 p3.3/adc3 v ssc p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 v ssa cvbs0 cvbs1 sync_filter iref p1.5/sda1 p1.4/scl1 p1.7/sda0 p1.6/scl0 p1.3/t1 p1.2/int0 p1.1/t0 p1.0/int1 v ddp reset xtalout xtalin oscgnd v ddc v ssp vsync hsync vds r g b v dda p3.4/pwm7 cor vpe frame 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
2000 feb 23 7 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.3 lqfp100 pin configuration. handbook, full pagewidth 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 p3.7 p0.4 n.c. p0.3 n.c. n.c. n.c. p0.2 p0.1 p0.0 n.c. n.c. p0.5 v ssp v ssc n.c. n.c. n.c. n.c. p3.3/adc3 p3.2/adc2 p3.1/adc1 n.c. p3.0/adc0 p2.7/pwm6 n.c. vds hsync p3.5 vsync n.c. n.c. n.c. p3.6 v ssp n.c. vpe_2 v ddc n.c. n.c. n.c. n.c. n.c. oscgnd xtalin xtalout n.c. reset n.c. v ddp 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p2.0/tpwm n.c. p2.6/pwm5 p2.5/pwm4 p2.4/pwm3 p2.3/pwm2 p2.2/pwm1 p2.1/pwm0 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. p1.5/sda1 p1.4/scl1 p1.7/sda0 p1.6/scl0 p1.3/t1 p1.2/int0 p1.1/t0 n.c. p1.0/int1 n.c. n.c. p0.6 p0.7 v ssa cvbs0 cvbs1 n.c. sync_filter iref n.c. n.c. n.c. n.c. n.c. frame vpe cor p3.4/pwm7 v dda b g r n.c. n.c. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 gsa001 saa55xx
2000 feb 23 8 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 6.2 pin description table 1 sdip52 and lqfp100 packages symbol pin type description sdip52 lqfp100 p2.0/tpwm 1 100 i/o port 2. 8-bit programmable bidirectional port with alternative functions. p2.0/tpwm is the output for the 14-bit high precision pwm; p2.1/pwm0 to p2.7/pwm6 are the outputs for the 6-bit pwms 0 to 6. p2.1/pwm0 2 93 i/o p2.2/pwm1 3 94 i/o p2.3/pwm2 4 95 i/o p2.4/pwm3 5 96 i/o p2.5/pwm4 6 97 i/o p2.6/pwm5 7 98 i/o p2.7/pwm6 8 1 i/o p3.0/adc0 9 2 i/o port 3. 8-bit programmable bidirectional port with alternative functions. p3.0/adc0 to p3.3/adc3 are the inputs for the software adc facility and p3.4/pwm7 is the output for the 6-bit pwm7. p3.5 to p3.7 have no alternative functions and are only available with the lqfp100 package. p3.1/adc1 10 4 i/o p3.2/adc2 11 5 i/o p3.3/adc3 12 6 i/o p3.4/pwm7 30 44 i/o p3.5 - 54 i/o p3.6 - 59 i/o p3.7 - 25 i/o v ssc 13 11 - core ground p0.0 14 16 i/o port 0. 8-bit programmable bidirectional port. p0.5 and p0.6 have 8 ma current sinking capability for direct drive of leds. p0.1 15 17 i/o p0.2 16 18 i/o p0.3 17 22 i/o p0.4 18 24 i/o p0.5 19 13 i/o p0.6 20 28 i/o p0.7 21 29 i/o v ssa 22 30 - analog ground cvbs0 23 31 i composite video input. a positive-going 1 v (peak-to-peak) input is required. cvbs1 24 32 i connected via a 100 nf capacitor sync_filter 25 34 i cvbs sync ?lter input. this pin should be connected to v ssa via a 100 nf capacitor. iref 26 35 i reference current input for analog circuits, connected to v ssa via a 24 k w resistor. frame 27 41 o de-interlace output synchronized with the vsync pulse to produce a non-interlaced display by adjustment of the vertical de?ection circuits. vpe 28 42 i otp programming voltage
2000 feb 23 9 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx cor 29 43 o open-drain, active low output which allows selective contrast reduction of the tv picture to enhance a mixed mode display. v dda 31 45 - +3.3 v analog power supply b 32 46 o pixel rate output of the blue colour information g 33 47 o pixel rate output of the green colour information r 34 48 o pixel rate output of the red colour information vds 35 52 o video/data switch push-pull output for dot rate fast blanking hsync 36 53 i schmitt triggered input for a ttl-level version of the horizontal sync pulse; the polarity of this pulse is programmable by register bit txt1.h polarity. vsync 37 55 i schmitt triggered input for a ttl-level version of the vertical sync pulse; the polarity of this pulse is programmable by register bit txt1.v polarity. v ssp 38 12, 60 - periphery ground v ddc 39 63 - +3.3 v core power supply oscgnd 40 69 - crystal oscillator ground xtalin 41 70 i 12 mhz crystal oscillator input xtalout 42 71 o 12 mhz crystal oscillator output reset 43 73 i if the reset input is high for at least 2 machine cycles (24 oscillator periods) while the oscillator is running, the device is reset; this pin should be connected to v ddp via a capacitor. v ddp 44 75 - +3.3 v periphery power supply p1.0/int1 45 76 i/o port 1. 8-bit programmable bidirectional port with alternative functions. p1.0/int1 is external interrupt 1 which can be triggered on the rising and falling edge of the pulse. p1.1/t0 is the counter/timer 0. p1.2/int0 is external interrupt 0. p1.3/t1 is the counter/timer 1. p1.6/scl0 is the serial clock input for the i 2 c-bus and p1.7/sda0 is the serial data port for the i 2 c-bus. p1.4/scl1 is the serial clock input for the i 2 c-bus and p1.5/sda1 is the serial data port for the i 2 c-bus. p1.1/t0 46 78 i/o p1.2/int0 47 79 i/o p1.3/t1 48 80 i/o p1.6/scl0 49 81 i/o p1.7/sda0 50 82 i/o p1.4/scl1 51 83 i/o p1.5/sda1 52 58 i/o vpe-2 - 62 i otp programming voltage n.c. - 3, 7 to 10,14, 15, 19 to 21, 23, 26, 27, 33, 36 to 40, 49 to 51, 56 to 58, 61, 64 to 68, 72, 74, 77, 85 to 92, 99 - not connected symbol pin type description sdip52 lqfp100
2000 feb 23 10 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 7 microcontroller the functionality of the microcontroller used on this device is described here with reference to the industry standard 80c51 microcontroller. a full description of its functionality can be found in handbook ic20, 80c51-based 8-bit microcontrollers. 7.1 microcontroller features 80c51 microcontroller core standard instruction set and timing 1 m s machine cycle maximum 128k 8-bit program rom maximum of 12k 8-bit auxiliary ram interrupt controller for individual enable/disable with two level priority two 16-bit timer/counter registers watchdog timer auxiliary ram page pointer 16-bit data pointer idle and power-down mode 29 general i/o lines eight 6-bit pulse width modulator (pwm) outputs for control of tv analog signals one 14-bit pwm for voltage synthesis tuner (vst) control 8-bit adc with 4 multiplexed inputs 2 high current outputs for directly driving leds etc. i 2 c byte level bus interface with dual ports. 8 memory organization the device has the capability of a maximum of 128-kbyte program rom and 12-kbyte data ram internally. 8.1 rom bank switching the 64-kbyte device has a continuous address space from 0 to 64 kbytes. the 128-kbyte memory is arranged in four banks of 32 kbytes. one of the 32-kbyte banks is common and is always addressable. the other three banks (bank 0, bank 1 and bank 2) can be accessed by selecting the right bank via the sfr rombk bits; see table 2. the rom bank switching is handled and supported by the compiler and linker development tools. table 2 rom bank selection 8.2 security bits - program and verify saa55xx devices have a set of security bits allied with each section of the device, i.e. program rom, character rom and packet 26 rom. the security bits are used to prevent the rom from being overwritten once programmed, and also the contents being verified once programmed. the security bits are one-time programmable and cannot be erased. the saa55xx memory and security bits are structured as shown in fig.5. the saa55xx security bits are set as shown in fig.6 for production programmed devices and are set as shown in fig.7 for production blank devices. 8.3 ram organisation the internal data ram is organised into two areas, data memory and special function registers (sfrs) as shown in fig.8. 8.4 data memory the data memory is 256 8 bits and occupies the address range 00h to ffh when using indirect addressing and 00h to 7fh when using direct addressing. the sfrs occupy the address range 80h to ffh and are accessible using direct addressing only. the lower 128 bytes of data memory are mapped as shown in fig.9. the lowest 24 bytes are grouped into 4 banks of 8 registers, the next 16 bytes above the register banks form a block of bit addressable memory space. the upper 128 bytes is not allocated for any special area or functions. table 3 bank selection rombk1 rombk0 0 to 32-kbyte 32 to 64-kbyte 0 0 common bank 0 0 1 common bank 1 1 0 common bank 2 1 1 reserved reserved rs1 rs0 bank 0 0 bank 0 0 1 bank 1 1 0 bank 2 1 1 bank 3
2000 feb 23 11 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.4 rom bank switching memory map. handbook, halfpage mbk952 7fffh 0000h common (32-kbyte) ffffh 8000h bank 1 (32-kbyte) ffffh 8000h bank 2 (32-kbyte) ffffh 8000h bank 0 (32-kbyte) fig.5 memory and security bit structures. handbook, full pagewidth mbk953 program rom memory user rom programming (enable/disable) verify (enable/disable) security bits interaction user rom (128k x 8-bit) character rom user rom (9k x 12-bit) packet 26 rom user rom (4k x 8-bit) user rom programming (enable/disable) verify (enable/disable) user rom programming (enable/disable) verify (enable/disable)
2000 feb 23 12 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.6 security bits for production devices. handbook, full pagewidth mbk954 program rom memory user rom programming (enable/disable) verify (enable/disable) disabled enabled disabled enabled disabled enabled security bits set character rom packet 26 rom fig.7 security bits for production blank devices. handbook, full pagewidth mbk955 program rom memory user rom programming (enable/disable) verify (enable/disable) enabled enabled enabled enabled enabled enabled security bits set character rom packet 26 rom
2000 feb 23 13 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.8 internal data memory. handbook, halfpage mbk956 accessible by indirect addressing only data memory ffh upper 128 bytes lower 128 bytes 80h 7fh 00h special function registers accessible by direct and indirect addressing accessible by direct addressing only fig.9 lower 128 bytes of internal ram. handbook, halfpage mgm677 r7 r0 07h 0 r7 r0 0fh 08h r7 r0 17h 10h r7 r0 1fh 18h 2fh 7fh 20h 30h bit-addressable space (bit addresses 00h to 7fh) 4 banks of 8 registers (r0 to r7)
2000 feb 23 14 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 8.5 sfr memory the special function register (sfr) space is used for port latches, timer, peripheral control, acquisition control, display con trol, etc. these registers can only be accessed by direct addressing. sixteen of the addresses in the sfr space are both bit and byte addressable. the bit addressable sfrs are those whose address ends in 0h or 8h. a summary of the sfr map in address order is shown in table 4. a description of each of the sfr bits is shown in table 5 which presents the sfrs in alphabetical order. table 4 sfr memory map add r/w name 7 6 5 4 3 2 1 0 reset 80h r/w p0 p07 p06 p05 p04 p03 p02 p01 p00 ffh 81h r/w sp sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 07h 82h r/w dpl dpl7 dpl6 dpl5 dpl4 dpl3 dpl2 dpl1 dpl0 00h 83h r/w dph dph7 dph6 dph5 dph4 dph3 dph2 dph1 dph0 00h 87h r/w pcon 0 ard rfi wle gf1 gf0 pd idl 00h 88h r/w tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h 89h r/w tmod gate c/ tm1 m0gatec/ t m1 m0 00h 8ah r/w tl0 tl07 tl06 tl05 tl04 tl03 tl02 tl01 tl00 00h 8bh r/w tl1 tl17 tl16 tl15 tl14 tl13 tl12 tl11 tl10 00h 8ch r/w th0 th07 th06 th05 th04 th03 th02 th01 th00 00h 8dh r/w th1 th17 th16 th15 th14 th13 th12 th11 th10 00h 90h r/w p1 p17 p16 p15 p14 p13 p12 p11 p10 ffh 96h r/w p0cfga p0cfga7 p0cfga6 p0cfga5 p0cfga4 p0cfga3 p0cfga2 p0cfga1 p0cfga0 ffh 97h r/w p0cfgb p0cfgb7 p0cfgb6 p0cfgb5 p0cfgb4 p0cfgb3 p0cfgb2 p0cfgb1 p0cfgb0 00h 98h r/w sadb 0 0 0 dc_comp sad3 sad2 sad1 sad0 00h 9eh r/w p1cfga p1cfga7 p1cfga6 p1cfga5 p1cfga4 p1cfga3 p1cfga2 p1cfga1 p1cfga0 ffh 9fh r/w p1cfgb p1cfgb7 p1cfgb6 p1cfgb5 p1cfgb4 p1cfgb3 p1cfgb2 p1cfgb1 p1cfgb0 00h a0h r/w p2 p27 p26 p25 p24 p23 p22 p21 p20 ffh a6h r/w p2cfga p2cfga7 p2cfga6 p2cfga5 p2cfga4 p2cfga3 p2cfga2 p2cfga1 p2cfga0 ffh a7h r/w p2cfgb p2cfgb7 p2cfgb6 p2cfgb5 p2cfgb4 p2cfgb3 p2cfgb2 p2cfgb1 p2cfgb0 00h a8h r/w ie ea ebusy es2 ecc et1 ex1 et0 ex0 00h b0h r/w p3 p37 p36 p35 p34 p33 p32 p31 p30 ffh
2000 feb 23 15 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... b2h r/w txt18 not3 not2 not1 not0 0 0 bs1 bs0 00h b3h r/w txt19 ten tc2 tc1 tc0 0 0 ts1 ts0 00h b4h r/w txt20 drcs enable osd planes 0 0 osd lang enable osd lan2 osd lan1 osd lan0 00h b5h r/w txt21 disp lines1 disp lines0 char size1 char size0 i 2 c port 1 cc on i 2 c port 0 cc/txt 02h b6h r txt22 gpf7 gpf6 gpf5 gpf4 gpf3 gpf2 gpf1 1 xxh b7h r/w cclin 0 0 0 cs4 cs3 cs2 cs1 cs0 15h b8h r/w ip 0 pbusy pes2 pcc pt1 px1 pt0 px0 00h b9h r/w txt17 0 force acq1 force acq0 force disp1 force disp0 screen col2 screen col1 screen col0 00h bah r wss1 0 0 0 wss<3:0> error wss3 wss2 wss1 wss0 00h bbh r wss2 0 0 0 wss<7:4> error wss7 wss6 wss5 wss4 00h bch r wss3 wss<13:11> error wss13 wss12 wss11 wss<10:8> error wss10 wss9 wss8 00h beh r/w p3cfga 1 1 1 p3cfga4 p3cfga3 p3cfga2 p3cfga1 p3cfga0 ffh bfh r/w p3cfgb 0 0 0 p3cfgb4 p3cfgb3 p3cfgb2 p3cfgb1 p3cfgb0 00h c0h r/w txt0 x24 posn display x24 auto frame disable header roll display status row only disable frame vps on inv on 00h c1h r/w txt1 ext pkt off 8-bit acq off x26 off full field field polarity h polarity v polarity 00h c2h r/w txt2 acq bank req3 req2 req1 req0 sc2 sc1 sc0 00h c3h w txt3 --- prd4 prd3 prd2 prd1 prd0 00h c4h r/w txt4 osd bank enable quad width enable east/ west disable double height b mesh enable c mesh enable trans enable shadow enable 00h c5h r/w txt5 bkgnd out bkgnd in cor out cor in text out text in picture on out picture on in 03h add r/w name 7 6 5 4 3 2 1 0 reset
2000 feb 23 16 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... c6h r/w txt6 bkgnd out bkgnd in cor out cor in text out text in picture on out picture on in 03h c7h r/w txt7 status row top cursor on reveal bottom / t op double height box on 24 box on 1-23 box on 0 00h c8h r/w txt8 (reserved) 0 flicker st op on (reserved) 0 disable spanish pkt 26 received wss received wss on cvbs1/ cvbs0 00h c9h r/w txt9 cursor freeze clear memory a0 r4 r3 r2 r1 r0 00h cah r/w txt10 0 0 c5 c4 c3 c2 c1 c0 00h cbh r/w txt11 d7 d6 d5 d4 d3 d2 d1 d0 00h cch r txt12 525/ 625 sync spanish rom ver3 rom ver2 rom ver1 rom ver0 1 video signal quality xxxx xx1x cdh r/w txt14 0 0 0 - page3 page2 page1 page0 00h ceh r/w txt15 0 0 0 - block3 block2 block1 block0 00h d0h r/w psw c ac f0 rs1 rs0 ov - p 00h d2h r/w tdacl td7 td6 td5 td4 td3 td2 td1 td0 00h d3h r/w tdach tpwe 1 td13 td12 td11 td10 td9 td8 40h d4h r/w pwm7 pw7e 1 pw7v5 pw7v4 pw7v3 pw7v2 pw7v1 pw7v0 40h d5h r/w pwm0 pw0e 1 pw0v5 pw0v4 pw0v3 pw0v2 pw0v1 pw0v0 40h d6h r/w pwm1 pw1e 1 pw1v5 pw1v4 pw1v3 pw1v2 pw1v1 pw1v0 40h d7h r ccdat1 ccd17 ccd16 ccd15 ccd14 ccd13 ccd12 ccd11 ccd10 00h d8h r/w s1con cr2 ensi sta sto si aa cr1 cr0 00h d9h r s1sta stat4 stat3 stat2 stat1 stat0 0 0 0 f8h dah r/w s1dat dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 00h dbh r/w s1adr adr6 adr5 adr4 adr3 adr2 adr1 adr0 gc 00h dch r/w pwm3 pw3e 1 pw3v5 pw3v4 pw3v3 pw3v2 pw3v1 pw3v0 40h ddh r/w pwm4 pw4e 1 pw4v5 pw4v4 pw4v3 pw4v2 pw4v1 pw4v0 40h deh r/w pwm5 pw5e 1 pw5v5 pw5v4 pw5v3 pw5v2 pw5v1 pw5v0 40h dfh r/w pwm6 pw6e 1 pw6v5 pw6v4 pw6v3 pw6v2 pw6v1 pw6v0 40h e0h r/w acc acc7 acc6 acc5 acc4 acc3 acc2 acc1 acc0 00h add r/w name 7 6 5 4 3 2 1 0 reset
2000 feb 23 17 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... e4h r/w pwm2 pw2e 1 pw2v5 pw2v4 pw2v3 pw2v2 pw2v1 pw2v0 40h e7h r ccdat2 ccd27 ccd26 ccd25 ccd24 ccd23 ccd22 ccd21 ccd20 00h e8h r/w sad vhi ch1 ch0 st sad7 sad6 sad5 sad4 00h f0h r/w b b7 b6 b5 b4 b3 b2 b1 b0 00h f8h r/w txt13 vps received pag e clearing 525 display 525 text 625 text pkt 8/30 fastext 0 xxxx xxx0 fah r/w xramp xramp7 xramp6 xramp5 xramp4 xramp3 xramp2 xramp1 xramp0 00h fbh r/w rombk standby 0 0 0 0 0 rombk1 rombk0 00h feh r wdtkey wkey7 wkey6 wkey5 wkey4 wkey3 wkey2 wkey1 wkey0 00h ffh r/w wdt wdv7 wdv6 wdv5 wdv4 wdv3 wdv2 wdv1 wdv0 00h add r/w name 7 6 5 4 3 2 1 0 reset
2000 feb 23 18 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx table 5 sfr bit description bit function accumulator (acc) acc7 to acc0 accumulator value b register (b) b7 to b0 b register value cc data byte 1 (ccdat1) ccd17 to ccd10 closed caption ?rst data byte cc data byte 2 (ccdat2) ccd26 to ccd20 closed caption second data byte cc line (cclin) cs4 to cs0 closed caption slice line using 525-line number data pointer high byte (dph) dph7 to dph0 data pointer high byte, used with dpl to address auxiliary memory data pointer low byte (dpl) dpl7 to dpl0 data pointer low byte, used with dph to address auxiliary memory interrupt enable register (ie) ea disable all interrupts (logic 0), or use individual interrupt enable bits (logic 1) ebusy enable busy interrupt es2 enable i 2 c-bus interrupt ecc enable closed caption interrupt et1 enable timer 1 interrupt ex1 enable external interrupt 1 et0 enable timer 0 interrupt ex0 enable external interrupt 0 interrupt priority register (ip) pbusy priority ebusy interrupt pes2 priority es2 interrupt pcc priority ecc interrupt pt1 priority timer 1 interrupt px1 priority external interrupt 1 pt0 priority timer 0 interrupt px0 priority external interrupt 0 port 0 (p0) p07 to p00 port 0 i/o register connected to external pins
2000 feb 23 19 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx port 1 (p1) p17 to p10 port 1 i/o register connected to external pins port 2 (p2) p27 to p20 port 2 i/o register connected to external pins port 3 (p3) p37 to p30 port 3 i/o register connected to external pins; p37 to p35 are only available with the lqfp100 package. port 0 con?guration a (p0cfga) and port 0 con?guration b (p0cfgb) p0cfga<7:0> and p0cfgb<7:0> these two registers are used to con?gure port 0 pins. for example, the con?guration of port 0 pin 3 is controlled by using bit 3 in both p0cfga and p0cfgb. p0cfgb/p0cfga: 00 = p0.x in open-drain configuration 01 = p0.x in quasi-bidirectional configuration 10 = p0.x in high-impedance configuration 11 = p0.x in push-pull configuration port 1 con?guration a (p1cfga) and port 1 con?guration b (p1cfgb) p1cfga<7:0> and p1cfgb<7:0> these two registers are used to con?gure port 1 pins. for example, the con?guration of port 1 pin 3 is controlled by using bit 3 in both p1cfga and p1cfgb. p1cfgb/p1cfga: 00 = p1.x in open-drain configuration 01 = p1.x in quasi-bidirectional configuration 10 = p1.x in high-impedance configuration 11 = p1.x in push-pull configuration port 2 con?guration a (p2cfga) and port 2 con?guration b (p2cfgb) p2cfga<7:0> and p2cfgb<7:0> these two registers are used to con?gure port 2 pins. for example, the con?guration of port 2 pin 3 is controlled by using bit 3 in both p2cfga and p2cfgb. p2cfgb/p2cfga: 00 = p2.x in open-drain configuration 01 = p2.x in quasi-bidirectional configuration 10 = p2.x in high-impedance configuration 11 = p2.x in push-pull configuration port 3 con?guration a (p3cfga) and port 3 con?guration b (p3cfgb) p3cfga<7:0> and p3cfgb<7:0> these two registers are used to con?gure port 3 pins. for example, the con?guration of port 3 pin 3 is controlled by using bit 3 in both p3cfga and p3cfgb. p3cfgb/p3cfga: 00 = p3.x in open-drain configuration 01 = p3.x in quasi-bidirectional configuration 10 = p3.x in high-impedance configuration 11 = p3.x in push-pull configuration bit function
2000 feb 23 20 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx power control register (pcon) ard auxiliary ram disable bit, all movx instructions access the external data memory rfi disable ale during internal access to reduce radio frequency interference wle watchdog timer enable gf1 general purpose ?ag 1 gf0 general purpose ?ag 0 pd power-down mode activation bit idl idle mode activation bit program status word (psw) c carry bit ac auxiliary carry bit f0 ?ag 0 rs1 to rs0 register bank selector bits rs<1:0>: 00 = bank 0 (00h to 07h) 01 = bank 1 (08h to 0fh) 10 = bank 2 (10h to 17h) 11 = bank 3 (18h to 1fh) ov over?ow ?ag p parity bit pulse width modulator 0 control register (pwm0) pw0e activate this pwm and take control of respective port pin (logic 1) pw0v5 to pw0v0 pulse width modulator high time pulse width modulator 1 control register (pwm1) pw1e activate this pwm (logic 1) pw1v5 to pw1v0 pulse width modulator high time pulse width modulator 2 control register (pwm2) pw2e activate this pwm (logic 1) pw2v5 to pw2v0 pulse width modulator high time pulse width modulator 3 control register (pwm3) pw3e activate this pwm (logic 1) pw3v5 to pw3v0 pulse width modulator high time pulse width modulator 4 control register (pwm4) pw4e activate this pwm (logic 1) pw4v5 to pw4v0 pulse width modulator high time bit function
2000 feb 23 21 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx pulse width modulator 5 control register (pwm5) pw5e activate this pwm (logic 1) pw5v5 to pw5v0 pulse width modulator high time pulse width modulator 6 control register (pwm6) pw6e activate this pwm (logic 1) pw6v5 to pw6v0 pulse width modulator high time pulse width modulator 7 control register (pwm7) pw7e activate this pwm (logic 1) pw7v5 to pw7v0 pulse width modulator high time rom bank (rombk) rombk1 to rombk0 rom bank selection bits; rombk<1:0>: 00 = bank 0 01 = bank 1 10 = bank 2 11 = reserved standby standby activation bit i 2 c-bus slave address register (s1adr) adr6 to adr0 i 2 c-bus slave address to which the device will respond gc enable i 2 c-bus general call address (logic 1) i 2 c-bus control register (s1con) cr2 to cr0 clock rate bits; cr<2:0>: 000 = 100 khz bit rate 001 = 3.75 khz bit rate 010 = 150 khz bit rate 011 = 200 khz bit rate 100 = 25 khz bit rate 101 = 1.875 khz bit rate 110 = 37.5 khz bit rate 111 = 50 khz bit rate ensi enable i 2 c-bus interface (logic 1) sta start ?ag. when this bit is set in slave mode, the hardware checks the i 2 c-bus and generates a start condition if the bus is free or after the bus becomes free. if the device operates in master mode it will generate a repeated start condition. sto stop ?ag. if this bit is set in a master mode a stop condition is generated. a stop condition detected on the i 2 c-bus clears this bit. this bit may also be set in slave mode in order to recover from an error condition. in this case no stop condition is generated to the i 2 c-bus, but the hardware releases the sda and scl lines and switches to the not selected receiver mode. the stop ?ag is cleared by the hardware. bit function
2000 feb 23 22 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx si serial interrupt ?ag. this ?ag is set and an interrupt request is generated, after any of the following events occur: a start condition is generated in master mode the own slave address has been received during aa = 1 the general call address has been received while s1adr.gc and aa = 1 a data byte has been received or transmitted in master mode (even if arbitration is lost) a data byte has been received or transmitted as selected slave a stop or start condition is received as selected slave receiver or transmitter. while the si ?ag is set, scl remains low and the serial transfer is suspended. si must be reset by software. aa assert acknowledge ?ag. when this bit is set, an acknowledge is returned after any one of the following conditions: own slave address is received general call address is received (s1adr.gc = 1) a data byte is received, while the device is programmed to be a master receiver a data byte is received, while the device is selected slave receiver. when the bit is reset, no acknowledge is returned. consequently, no interrupt is requested when the own address or general call address is received. i 2 c-bus data register (s1dat) dat7 to dat0 i 2 c-bus data i 2 c-bus status register (s1sta) stat4 to stat0 i 2 c-bus interface status software adc register (sad) vhi analog input voltage greater than dac voltage (logic 1) ch1 to ch0 adc input channel select bits; ch<1:0>: 00 = adc3 01 = adc0 10 = adc1 11 = adc2 st (1) initiate voltage comparison between adc input channel and sad value sad7 to sad4 4 msbs of dac input word software adc control register (sadb) dc_comp enable dc comparator mode (logic 1) sad3 to sad0 4 lsbs of sad value stack pointer (sp) sp7 to sp0 stack pointer value bit function
2000 feb 23 23 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx timer/counter control register (tcon) tf1 timer 1 over?ow ?ag. set by hardware on timer/counter over?ow. cleared by hardware when processor vectors to interrupt routine. tr1 timer 1 run control bit. set/cleared by software to turn timer/counter on/off. tf0 timer 0 over?ow ?ag. set by hardware on timer/counter over?ow. cleared by hardware when processor vectors to interrupt routine. tr0 timer 0 run control bit. set/cleared by software to turn timer/counter on/off. ie1 interrupt 1 edge ?ag. both edges generate ?ag. set by hardware when external interrupt edge detected. cleared by hardware when interrupt processed. it1 interrupt 1 type control bit. set/cleared by software to specify edge/low level triggered external interrupts. ie0 interrupt 0 edge l ?ag. set by hardware when external interrupt edge detected. cleared by hardware when interrupt processed. it0 interrupt 0 type ?ag. set/cleared by software to specify falling edge/low level triggered external interrupts. 14-bit pwm msb register (tdach) tpwe activate this 14-bit pwm (logic 1) td13 to td8 6 msbs of 14-bit number to be output by the 14-bit pwm 14-bit pwm lsb register (tdacl) td7 to td0 8 lsbs of 14-bit number to be output by the 14-bit pwm timer 0 high byte (th0) th07 to th00 8 msbs of timer 0 16-bit counter timer 1 high byte (th1) th17 to th10 8 msbs of timer 1 16-bit counter timer 0 low byte (tl0) tl07 to tl00 8 lsbs of timer 0 16-bit counter timer 1 low byte (tl1) tl17 to tl10 8 lsbs of timer 1 16-bit counter timer/counter mode control (tmod) gate gating control timer/counter 1 c/ t counter/timer 1 selector m1 to m0 mode control bits timer/counter 1; m<1:0>: 00 = 8-bit timer or 8-bit counter with divide-by-32 prescaler 01 = 16-bit time interval or event counter 10 = 8-bit time interval or event counter with automatic reload upon overflow; reload value stored in th1 11 = stopped gate gating control timer/counter 0 c/ t counter/timer 0 selector bit function
2000 feb 23 24 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx m1 to m0 mode control bits timer/counter 0; m<1:0> 00 = 8-bit timer or 8-bit counter with divide-by-32 prescaler 01 = 16-bit time interval or event counter 10 = 8-bit time interval or event counter with automatic reload upon overflow; reload value stored in th0 11 = one 8-bit time interval or event counter and one 8-bit time interval counter text register 0 (txt0) x24 posn store packet 24 in extension packet memory (logic 0) or page memory (logic 1) display x24 display x24 from page memory (logic 0) or extension packet memory (logic 1) auto frame frame output switched off automatically if any video displayed (logic 1) disable header roll disable writing of rolling headers and time into memory (logic 1) display status row only display row 24 only (logic 1) disable frame frame output always low (logic 1) vps on enable capture of vps data (logic 1) inv on enable capture of inventory page in block 8 (logic 1) text register 1 (txt1) ext pkt off disable acquisition of extension packets (logic 1) 8-bit disable checking of packets 0 to 24 written into memory (logic 1) acq off disable writing of data into display memory (logic 1) x26 off disable automatic processing of x/26 data (logic 1) full field acquire data on any tv line (logic 1) field polarity vsync pulse in second half of line during even ?eld (logic 1) h polarity hsync reference edge is negative going (logic 1) v polarity vsync reference edge is negative going (logic 1) text register 2 (txt2) acq bank select acquisition bank 1 (logic 1) req3 to req0 page request sc2 to sc0 start column of page request text register 3 (txt3) prd4 to prd0 page request data text register 4 (txt4) osd bank enable alternate osd location available via graphic attribute, additional 32 locations (logic 1) quad width enable enable display of quadruple width characters (logic 1) east/ west eastern language selection of character codes a0h to ffh (logic 1) disable double height disable normal decoding of double height characters (logic 1) b mesh enable enable meshing of black background (logic 1) c mesh enable enable meshing of coloured background (logic 1) trans enable display black background as video (logic 1) shadow enable display shadow/fringe (default se black) (logic 1) bit function
2000 feb 23 25 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx text register 5 (txt5) bkgnd out background colour displayed outside teletext boxes (logic 1) bkgnd in background colour displayed inside teletext boxes (logic 1) cor out cor active outside teletext and osd boxes (logic 1) cor in cor active inside teletext and osd boxes (logic 1) text out text displayed outside teletext boxes (logic 1) text in text displayed inside teletext boxes (logic 1) picture on out video displayed outside teletext boxes (logic 1) picture on in video displayed inside teletext boxes (logic 1) text register 6 (txt6) bkgnd out background colour displayed outside teletext boxes (logic 1) bkgnd in background colour displayed inside teletext boxes (logic 1) cor out cor active outside teletext and osd boxes (logic 1) cor in cor active inside teletext and osd boxes (logic 1) text out text displayed outside teletext boxes (logic 1) text in text displayed inside teletext boxes (logic 1) picture on out video displayed outside teletext boxes (logic 1) picture on in video displayed inside teletext boxes (logic 1) text register 7 (txt7) status row top display memory row 24 information above teletext page (on display row 0) (logic 1) cursor on display cursor at position given by txt9 and txt10 (logic 1) reveal display characters in area with conceal attribute set (logic 1) bottom/ t op display memory rows 12 to 23 when double height height bit is set (logic 1) double height display each character as twice normal height (logic 1) box on 24 enable display of teletext boxes in memory row 24 (logic 1) box on 1 to 23 enable display of teletext boxes in memory row 1 to 23 (logic 1) box on 0 enable display of teletext boxes in memory row 0 (logic 1) text register 8 (txt8) flicker st op on disable flicker stopper circuitry (logic 1) disable spanish disable special treatment of spanish packet 26 characters (logic 1) pkt 26 received (2) packet 26 data has been processed (logic 1) wss received (2) wss data has been processed (logic 1) wss on enable acquisition of wss data (logic 1) cvbs1/ cvbs0 select cvbs1 as source for device (logic 1) bit function
2000 feb 23 26 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx text register 9 (txt9) cursor freeze lock cursor at current position (logic 1) clear memory (1) clear memory block pointed to by txt15 (logic 1) a0 access extension packet memory (logic 1) r4 to r0 (3) current memory row value text register 10 (txt10) c5 to c0 (4) current memory column value text register 11 (txt11) d7 to d0 data value written or read from memory location de?ned by txt9, txt10 and txt15 text register 12 (txt12) 625/525 sync 525-line cvbs signal is being received (logic 1) spanish spanish character set present (logic 1) rom ver3 to rom ver0 mask programmable identi?cation for character set video signal quality acquisition can be synchronized to cvbs (logic 1) text register 13 (txt13) vps received vps data (logic 1) page clearing software or power-on page clear in progress (logic 1) 525 display 525-line synchronisation for display (logic 1) 525 text 525-line wst being received (logic 1) 625 text 625-line wst being received (logic 1) pkt 8/30 packet 8/30/x(625) or packet 4/30/x(525) data detected (logic 1) fastext packet x/27 data detected (logic 1) text register 14 (txt14) page3 to page0 current display page text register 15 (txt15) block3 to block0 current micro block to be accessed by txt9, txt10 and txt11 text register 17 (txt17) force acq1 to force acq0 force acq<1:0>: 00 = automatic selection 01 = force 525 timing, force 525 teletext standard 10 = force 625 timing, force 625 teletext standard 11 = force 625 timing, force 525 teletext standard force disp1 to force disp0 force disp<1:0>: 00 = automatic selection 01 = force display to 525 mode (9 lines per row) 10 = force display to 625 mode (10 lines per row) 11 = not valid (default to 625) bit function
2000 feb 23 27 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx screen col2 to screen col0 de?nes colour to be displayed instead of tv picture and black background; these bits are equivalent to the rgb components. screen col<2:0>: 000 = transparent 001 = clut entry 9 010 = clut entry 10 011 = clut entry 11 100 = clut entry 12 101 = clut entry 13 110 = clut entry 14 111 = clut entry 15 text register 18 (txt18) not3 to not0 national option table selection, maximum of 31 when used with east/ west bit bs1 to bs0 basic character set selection text register 19 (txt19) ten enable twist character set (logic 1) tc2 to tc0 language control bits (c12, c13 and c14) that has twisted character set ts1 to ts0 twist character set selection text register 20 (txt20) drcs enable re-map column 9 to drcs in txt mode (logic 1) osd planes character code columns 8 and 9 de?ned as double plane characters (logic 1) osd lang enable enable use of osd lan<2:0> to de?ne language option for display, instead of c12, c13 and c14 osd lan2 to osd lan0 alternative c12, c13 and c14 bits for use with osd menus text register 21 (txt21) disp lines1 to disp lines0 the number of display lines per character row; disp lines<1:0>: 00 = 10 lines per character (defaults to 9 lines in 525 mode) 01 = 13 lines per character 10 = 16 lines per character 11 = reserved char size1 to char size0 character matrix size bits; char size<1:0>: 00 = 10 lines per character (matrix 12 10) 01 = 13 lines per character (matrix 12 13) 10 = 16 lines per character (matrix 12 16) 11 = reserved i 2 c port 1 enable i 2 c-bus port 1 selection (p1.5/sda1 and p1.4/scl1) (logic 1) ccon closed caption acquisition on (logic 1) i 2 c port 0 enable i 2 c-bus port 0 selection (p1.7/sda0 and p1.6/scl0) (logic 1) cc/txt display con?gured for cc mode (logic 1) bit function
2000 feb 23 28 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx notes 1. this flag is set by software and reset by hardware. 2. this flag is set by hardware and must be reset by software. 3. valid range txt mode 0 to 24. 4. valid range txt mode 0 to 39. 5. must be set to 55h to disable watchdog timer when active. text register 22 (txt22) gpf7 to gpf75 general purpose register, bits de?ned by mask programmable bits gpf4 1 to 10 pages available (logic 1) gpf3 pwm0, pwm1, pwm2 and pwm3 outputs routed to port 2.1 to port 2.4 respectively (logic 1) gpf2 closed caption acquisition available (logic 1) gpf1 text acquisition available (logic 1) watchdog timer (wdt) wdv7 to wdv0 watchdog timer period watchdog timer key (wdtkey) wkey7 to wkey0 (5) watchdog timer key wide screen signalling 1 (wss1) wss<3:0> error error in wss<3:0> (logic 1) wss3 to wss0 signalling bits to de?ne aspect ratio (group 1) wide screen signalling 2 (wss2) wss<7:4> error error in wss<7:4> (logic 1) wss7 to wss4 signalling bits to de?ne enhanced services (group 2) wide screen signalling 3 (wss3) wss<13:11> error error in wss<13:11> (logic 1) wss13 to wss11 signalling bits to de?ne reserved elements (group 4) wss<10:8> error error in wss<10:8> (logic 1) wss10 to wss8 signalling bits to de?ne subtitles (group 3) xramp xramp7 to xramp0 internal ram access upper byte address bit function
2000 feb 23 29 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 8.6 character set feature bits features available on the saa55xx devices are reflected in a specific area of the character rom. these sections of the character rom are mapped to two special function registers: txt22 and txt12. character rom address 09feh is mapped to sfr txt22 as shown in table . character rom address 09ffh is mapped to sfr txt12 as shown in table . table 6 character rom - txt22 mapping u = used; x = reserved table 7 description of character rom address 09feh bits table 8 character rom - txt12 mapping u = used; x = reserved table 9 description of character rom address 09ffh bits mapped items 11 10 9 8 7 6 5 4 3 2 1 0 character rom address 09feh xxxxxxxuuuux mapped to txt22 ---- 76543210 bit function 0 reserved; normally set to logic 1 1 1 = text acquisition available 0 = text acquisition not available 2 1 = closed caption acquisition available 0 = closed caption acquisition not available 3 1 = pwm0, pwm1, pwm2 and pwm3 output routed to port 2.1 to port 2.4 respectively 0 = pwm0, pwm1, pwm2 and pwm3 output routed to port 3.0 to port 3.3 respectively 4 1 = 10 page available 0 = 6 page available 5 to 11 reserved; normally set to logic 1 mapped items 11 10 9 8 7 6 5 4 3 2 1 0 character rom address 09ffh xxxxxxxuxxxx mapped to txt12 ------- 65432 bit function 4 1 = spanish character set present 0 = no spanish character set present 0 to 3, 5 to 11 reserved; normally all set to logic 1
2000 feb 23 30 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 8.7 external (auxiliary) memory the normal 80c51 external memory area has been mapped internally to the device, this means that the movx instruction accesses memory internal to the device. 8.7.1 a uxiliary ram page selection the auxiliary ram page pointer is used to select one of the 256 pages within the auxiliary ram, not all pages are allocated; refer to fig.11 for further detail. a page consists of 256 consecutive bytes. handbook, halfpage gsa084 display ram for closed caption (3) upper 32 kbytes lower 32 kbytes ffffh 845fh 8000h dynamically redefinable characters display registers 8bffh 8c00h 8800h 87ffh 87f0h clut 871fh 8700h display ram for text pages (2) data ram (1) 47ffh 4800h 7fffh 2000h 07ffh 0000h 84ffh 8460h additional data ram fig.10 auxiliary ram allocation. (1) amount of data ram depends on device. (2) amount of display ram depends on the device. (3) display ram for closed caption and text is shared.
2000 feb 23 31 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.11 indirect addressing of auxiliary ram. handbook, full pagewidth mbk958 sfr xramp = 00h ffh 00h sfr xramp = 01h ffh 00h 0000h 00ffh 0100h 01ffh sfr xramp = feh movx @ dptr,a movx a, @ dptr movx @ ri,a movx a, @ ri ffh 00h sfr xramp = ffh ffh 00h fe00h feffh ff00h ffffh 9 power-on reset an automatic reset can be obtained when v dd is turned on by connecting the reset pin to v ddp through a 10 m f capacitor, providing the v dd rise time does not exceed 1 ms, and the oscillator start-up time does not exceed 10 ms. to ensure correct initialisation, the reset pin must be held high long enough for the oscillator to settle following power-up, usually a few milli-seconds. once the oscillator is stable, a further 24 clocks are required to generate the reset (two machine cycles of the microcontroller). once the above reset condition has been detected an internal reset signal is triggered which remains active for 2048 clock cycles.
2000 feb 23 32 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 10 reduced power modes there are two power saving modes, idle and power-down, incorporated into the 10 page devices. there is an additional standby mode incorporated into the 1 page devices. when utilizing any mode, power to the device (v ddp ,v ddc and v dda ) should be maintained, since power saving is achieved by clock gating on a section by section basis. 10.1 idle mode during idle mode, acquisition, display and the cpu sections of the device are disabled. the following functions remain active: memory interface i 2 c-bus interface timer/counters watchdog timer pulse width modulators. to enter idle mode the idl bit in the pcon register must be set. the watchdog timer must be disabled prior to entering idle to prevent the device being reset. once in idle mode, the xtal oscillator continues to run, but the internal clock to the cpu, acquisition and display are gated out. however, the clocks to the memory interface, i 2 c-bus interface, timer/counters, watchdog timer and pulse width modulators are maintained. the cpu state is frozen along with the status of all sfrs, internal ram contents are maintained, as are the device output pin values. since the output values on rgb and vds are maintained the display output must be disabled before entering this mode. there are three methods available to recover from idle: assertion of an enabled interrupt will cause the idl bit to be cleared by hardware, thus terminating idle mode. the interrupt is serviced, and following the instruction reti, the next instruction to be executed will be the one after the instruction that put the device into idle mode. a second method of exiting idle is via an interrupt generated by the sad dc compare circuit. when the device is configured in this mode, detection of an analog threshold at the input to the sad may be used to trigger wake-up of the device i.e. tv front panel key-press. as above, the interrupt is serviced, and following the instruction reti, the next instruction to be executed will be the one following the instruction that put the device into idle. the third method of terminating idle mode is with an external hardware reset. since the oscillator is running, the hardware reset need only be active for two machine cycles (24 clocks at 12 mhz) to complete the reset operation. reset defines all sfrs and display memory to a predefined state, but maintains all other ram values. code execution commences with the program counter set to 0000. 10.2 power-down mode in power-down mode the xtal oscillator is stopped. the contents of all sfrs and data memory are maintained, however, the contents of the auxiliary/display memory are lost. the port pins maintain the values defined by their associated sfrs. since the output values on rgb and vds are maintained the display output must be made inactive before entering power-down mode. the power-down mode is activated by setting the pd bit in the pcon register. it is advised to disable the watchdog timer prior to entering power-down. there are three methods of exiting power-down: an external interrupt provides the first mechanism for waking from power-down. since the clock is stopped, external interrupts need to be set level sensitive prior to entering power-down. the interrupt is serviced, and following the instruction reti, the next instruction to be executed will be the one after the instruction that put the device into power-down mode. a second method of exiting power-down is via an interrupt generated by the sad dc compare circuit. when the device is configured in this mode, detection of a certain analog threshold at the input to the sad may be used to trigger wake-up of the device i.e. tv front panel key-press. as above, the interrupt is serviced, and following the instruction reti, the next instruction to be executed will be the one following the instruction that put the device into power-down. the third method of terminating the power-down mode is with an external hardware reset. reset defines all sfrs and display memory, but maintains all other ram values. code execution commences with the program counter set to 0000.
2000 feb 23 33 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 10.3 standby mode this mode is only available on 1 page devices. when standby mode is entered both acquisition and display sections are disabled. the following functions remain active: 80c51 core memory interface i 2 c-bus interface timer/counters watchdog timer software adc pulse width modulators to enter standby mode, the standby control bit in the rombank sfr (bit 7) must be set. it can be used in conjunction with either idle or power-down modes to switch between power saving modes. this mode enables the 80c51 core to decode either ir remote commands or receive i 2 c-bus commands without the device being fully powered. the standby state is maintained upon exit from either the idle mode or power-down mode. no wake-up from standby is necessary as the 80c51 core remains operational. since the output values on rgb and vds are maintained the display output must be disabled before entering this mode. 11 i/o facility 11.1 i/o ports the saa55xx devices have 29 i/o lines, each is individually addressable, or form 3 parallel 8-bit addressable ports which are port 0, port 1 and port 2. port 3 has 5-bit parallel i/o only. 11.2 port type all individual ports can be programmed to function in one of four i/o configurations: open-drain, quasi-bidirectional, high-impedance and push-pull. the i/o configuration is selected using two associated port configuration registers: pncfga and pncfgb (where n = port number 0, 1, 2 or 3); see table 5. 11.2.1 o pen - drain the open-drain configuration can be used for bidirectional operation of a port. it requires an external pull-up resistor, the pull-up voltage has a maximum value of 5.5 v, to allow connection of the device into a 5 v environment. the i 2 c-bus ports (p1.4, p1.5, p1.6 and p1.7) can only be configured as open-drain. 11.2.2 q uasi - bidirectional the quasi-bidirectional configuration is a combination of open-drain and push-pull. it requires an external pull-up resistor to v ddp (normally 3.3 v). when a signal transition from low-to-high is output from the device, the pad is put into push-pull configuration for one clock cycle (166 ns) after which the pad goes into open-drain configuration. this configuration is used to speed up the edges of signal transitions. this is the default mode of operation of the pads after reset. 11.2.3 h igh - impedance the high-impedance configuration can be used for input only operation of the port. when using this configuration the two output transistors are turned off. 11.2.4 p ush - pull the push-pull configuration can be used for output only. in this mode the signal is driven to either 0 v or v ddp , which is nominally 3.3 v. 11.3 port alternative functions ports 1, 2 and 3 are shared with alternative functions to enable control of external devices and circuitry. the alternative functions are enabled by setting the appropriate sfr and also writing a logic 1 to the port bit that the function occupies. 11.4 led support port pins p0.5 and p0.6 have a 8 ma current sinking capability to enable leds in series with current limiting resistors to be driven directly, without the need for additional buffering circuitry.
2000 feb 23 34 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 12 interrupt system the device has 7 interrupt sources, each of which can be enabled or disabled. when enabled each interrupt can be assigned one of two priority levels. there are four interrupts that are common to the 80c51, two of these are external interrupts (ex0 and ex1) and the other two are timer interrupts (et0 and et1). in addition to the conventional 80c51 interrupts, two application specific interrupts are incorporated internal to the device which have following functionality: closed caption data ready interrupt (ecc). this interrupt is generated when the device is configured in closed caption acquisition mode. the interrupt is activated at the end of the currently selected slice line as defined in the cclin sfr. display busy interrupt (ebusy). an interrupt is generated when the display enters either a horizontal or vertical blanking period. i.e. indicates when the microcontroller can update the display ram without causing undesired effects on the screen. this interrupt can be configured in one of two modes using the mmr configuration register (address 87ffh, bit txt/v). C text display busy. an interrupt is generated on each active horizontal display line when the horizontal blanking period is entered. C vertical display busy. an interrupt is generated on each vertical display field when the vertical blanking period is entered. 12.1 interrupt enable structure each of the individual interrupts can be enabled or disabled by setting or clearing the relevant bit in the interrupt enable sfr(ie). all interrupt sources can also be globally disabled by clearing the ea bit (ie.7). the interrupt structure is shown in fig.12. 12.2 interrupt enable priority each interrupt source can be assigned one of two priority levels. the interrupt priorities are defined by the interrupt priority register (ip). a low priority interrupt can be interrupted by a high priority interrupt, but not by another low priority interrupt. a high priority interrupt can not be interrupted by any other interrupt source. if two requests of different priority levels are received simultaneously, the request with the highest priority level is serviced. if requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus, within each priority level there is a second priority structure determined by the polling sequence as defined in table 10. table 10 interrupt priority (within same level) 12.3 interrupt vector address the processor acknowledges an interrupt request by executing a hardware generated lcall to the appropriate servicing routine. the interrupt vector addresses for each source are shown in table 10. 12.4 level/edge interrupt the external interrupt can be programmed to be either level-activated or transition-activated by setting or clearing the it0/it1 bits in the timer control sfr (tcon). table 11 external interrupt activation the external interrupt int1 differs from the standard 80c51 interrupt in that it is activated on both edges when in edge sensitive mode. this is to allow software pulse width measurement for handling remote control inputs. source priority within level interrupt vector ex0 highest 0003h et0 - 000bh ex1 - 0013h et1 - 001bh ecc - 0023h es2 - 002bh ebusy lowest 0033h itx level edge 0 active low 1 - into = negative edge inti = positive and negative edge
2000 feb 23 35 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.12 interrupt structure. handbook, full pagewidth mbk959 priority control sfr ip < 0:6 > global enable sfr ie.7 l1 h1 highest priority level 0 highest priority level 1 l2 h2 l3 ex0 h3 l4 h4 l5 h5 l6 h6 source enable sfr ie < 0:6 > interrupt source l7 h7 lowest priority level 0 lowest priority level 1 et0 ex1 et1 ecc es2 ebusy
2000 feb 23 36 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 13 timer/counter two 16-bit timers/counters are incorporated timer 0 and timer 1. both can be configured to operate as either timers or event counters. in timer mode, the register is incremented on every machine cycle. it is therefore counting machine cycles. since the machine cycle consists of 12 oscillator periods, the count rate is 1 12 f osc = 1 mhz. in counter mode, the register is incremented in response to a negative transition at its corresponding external pin t0 or t1. since the pins t0 and t1 are sampled once per machine cycle it takes two machine cycles to recognise a transition, this gives a maximum count rate of 1 24 f osc = 0.5 mhz. there are six special function registers used to control the timers/counters. these are: tcon, tmod, tl0, th0, tl1 and th1. the timer/counter function is selected by control bits c/t in the timer mode sfr(tmod). these two timer/counters have four operating modes, which are selected by bit-pairs (m1 and m0) in tmod. detail of the modes of operation is given in handbook ic20, 80c51-based 8-bit microcontrollers. tl0 and th0 are the actual timer/counter registers for timer 0. tl0 is the low byte and th0 is the high byte. tl1 and th1 are the actual timer/counter registers for timer 1. tl1 is the low byte and th1 is the high byte. 14 watchdog timer the watchdog timer is a counter that once in an overflow state forces the microcontroller into a reset condition. the purpose of the watchdog timer is to reset the microcontroller if it enters an erroneous processor state (possibly caused by electrical noise or rfi) within a reasonable period of time. when enabled, the watchdog circuitry will generate a system reset if the user program fails to reload the watchdog timer within a specified length of time known as the watchdog interval (wi). the watchdog timer consists of an 8-bit counter with an 11-bit prescaler. the prescaler is fed with a signal whose frequency is 1 12 f osc (1 mhz for 12 mhz oscillator). the 8-bit timer is incremented every t seconds where: 14.1 watchdog timer operation the watchdog operation is activated when the wle bit in the power control sfr (pcon) is set. the watchdog can be disabled by software by loading the value 55h into the watchdog timer key sfr (wdtkey). this must be performed before entering idle/power-down mode to prevent exiting the mode prematurely. once activated the watchdog timer sfr (wdt) must be reloaded before the timer overflows. the wle bit must be set to enable loading of the wdt sfr, once loaded the wle bit is reset by hardware, this is to prevent erroneous software from loading the wdt sfr. the value loaded into the wdt defines the watchdog interval (wi). the range of intervals is from wdt = 00h which gives 524 ms to wdt = ffh which gives 2.048 ms. 15 pulse width modulators the device has eight 6-bit pulse width modulated (pwm) outputs for analog control of e.g. volume, balance, bass, treble, brightness, contrast, hue and saturation. the pwm outputs generate pulse patterns with a repetition rate of 21.33 m s, with the high time equal to the pwm sfr value multiplied by 0.33 m s. the analog value is determined by the ratio of the high time to the repetition time, a dc voltage proportional to the pwm setting is obtained by means of an external integration network (low-pass filter). 15.1 pwm control the relevant pwm is enabled by setting the pwm enable bit pwxe in the pwmx control register (where x = 0 to 7). the high time is defined by the value pwxv<5:0>. t 12 2048 1 f osc --------- 12 2048 1 12 10 6 --------------------- - 2.048 ms = = = wi 256 wdt C () t 256 wdt C () 2.048 ms = =
2000 feb 23 37 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 15.2 tuning pulse width modulator (tpwm) the device has a single 14-bit pwm that can be used for voltage synthesis tuning. the method of operation is similar to the normal pwm except that the repetition period is 42.66 m s. 15.2.1 tpwm control two sfrs are used to control the tpwm, they are tdacl and tdach. the tpwm is enabled by setting the tpwe bit in the tdach sfr. the most significant bits td<13:7> alter the high period between 0 and 42.33 m s. the 7 least significant bits td<6:0> extend certain pulses by a further 0.33 m s. e.g. if td<6:0> = 01h then 1 in 128 periods will be extended by 0.33 m s, if td<6:0> = 02h then 2 in 128 periods will be extended. the tpwm will not start to output a new value until tdach has been written to. therefore, if the value is to be changed, tdacl should be written before tdach. 15.3 software adc (sad) four successive approximation analog-to-digital converters can be implemented in software by making use of the on-board 8-bit digital-to-analog converter and analog comparator. 15.3.1 sad control the control of the required analog input is done using the channel select bits ch<1:0> in the sad sfr, this selects the required analog input to be passed to one of the inputs of the comparator. the second comparator input is generated by the dac whose value is set by the bits sad<7:0> in the sad and sadb sfrs. a comparison between the two inputs is made when the start compare bit st in the sad sfr is set, this must be at least one instruction cycle after the sad<7:0> value has been set. the result of the comparison is given on vhi one instruction cycle after the setting of st. 15.3.2 sad input voltage the external analog voltage that is used for comparison with the internally generated dac voltage does not have the same voltage range. the dac has a lower reference level of v ssa and an upper reference level of v ssp . the resolution of the dac voltage with a nominal value is 3.3 256 ? 13 mv. the external analog voltage has a lower value equivalent to v ssa and an upper value equivalent to v ddp - v tn , where v tn is the threshold voltage for an nmos transistor. the reason for this is that the input pins for the analog signals (p3.0 to p3.3) are 5 v tolerant for normal port operations, i.e. when not used as analog input. to protect the analog multiplexer and comparator circuitry from the 5 v, a series transistor is used to limit the voltage. this limiting introduces a voltage drop equivalent to v tn ( ? 0.6 v) on the input voltage. the maximum value of v in is 0.75 v, therefore for worst case calculations, the maximum input to the sad should be calculated as v dd(min) = - 0.75 v. therefore, for an input voltage in the range v ddp to v ddp - v tn the sad returns the same comparison value. 15.3.3 sad dc c omparator mode the sad module incorporates a dc comparator mode which is selected using the dc_comp control bit in the sadb sfr. this mode enables the microcontroller to detect a threshold crossing at the input to the selected analog input pin (p3.0/adc0, p3.1/adc1, p3.2/adc2 or p3.3/adc3) of the software adc. a level sensitive interrupt is generated when the analog input voltage level at the pin falls below the analog output level of the sad dac. this mode is intended to provide the device with a wake-up mechanism from power-down or idle mode when a key-press on the front panel of the tv is detected. the following software sequence should be used when utilizing this mode for power-down or idle mode: 1. disable int1 using the ie sfr. 2. set int1 to level sensitive using the tcon sfr. 3. set the dac digital input level to the desired threshold level using sad/sadb sfrs and select the required input pin (p3.0/adc0, p3.1/adc1, p3.2/adc2 or p3.3/adc3) using ch<1:0> in the sad sfr. 4. enter dc compare mode by setting the dc_comp enable bit in the sadb sfr. 5. enable int1 using the ie sfr. 6. enter power-down/idle mode. upon wake-up the sad should be restored to its conventional operating mode by disabling the dc_comp control bit.
2000 feb 23 38 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.13 sad block diagram. handbook, halfpage mbk960 mux 4 : 1 adc0 adc1 adc2 adc3 ch < 1:0 > sad < 3:0 > sadb < 3:0 > v ddp vhi 8-bit dac
2000 feb 23 39 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 16 i 2 c-bus serial i/o the i 2 c-bus consists of a serial data line (sda) and a serial clock line (scl). the definition of the i 2 c-bus protocol can be found in reference 2. the device operates in four modes master transmitter master receiver slave transmitter slave receiver. the microcontroller peripheral is controlled by the serial control sfr (s1con) and its status is indicated by the status sfr (s1sta). information is transmitted/received to/from the i 2 c-bus using the data sfr (s1dat) and the slave address sfr (s1adr) is used to configure the slave address of the peripheral. the byte level i 2 c-bus serial port is identical to the i 2 c-bus serial port on the p8xc558, except for the clock rate selection bits cr<2:0>. the operation of the subsystem is described in detail in the p8xc558 data sheet. 16.1 i 2 c-bus port selection two i 2 c-bus ports are available scl0/sda0 and scl1/sda1. the selection of the port is done using txt21.i 2 c port 0 and txt21.i 2 c port 1. when the port is enabled, any information transmitted from the device goes onto the enabled port. any information transmitted to the device can only be acted on if the port is enabled. if both ports are enabled then data transmitted from the device is seen on both ports, however data transmitted to the device on one port can not be seen on the other port. 17 memory interface the memory interface controls access to the embedded dram, refreshing of the dram and page clearing. the dram is shared between data capture, display and microcontroller sections. the data capture section uses the dram to store acquired information that has been requested. the display reads from the dram information and converts it into rgb values. the microcontroller uses the dram as embedded auxiliary ram. 17.1 memory structure the memory is partitioned into two distinct areas, the dedicated auxiliary ram area, and the display ram area. the display ram area when not being used for data capture or display can be used as an extension to the auxiliary ram area. 17.1.1 a uxiliary ram the auxiliary ram is not initialized at power-up. the application software must initialize this auxiliary ram. the contents of the auxiliary ram are maintained during idle mode, but are lost if power-down mode is entered. 17.1.2 d isplay ram the display ram is initialised on power-up to a value of 20h throughout. the contents of the display ram are maintained when entering idle mode. if idle mode is exited using an interrupt then the contents are unchanged, if idle mode is exited using a reset then the contents are initialised to 20h. full closed caption display requires display ram from 8000h to 845fh. the memory from 846h to 84ffh (must be initialized by the application software) can be utilized as an extension to the dedicated contiguous auxiliary ram that occupies 0000h to 07ffh. 17.2 memory mapping the dedicated auxiliary ram area occupies 2 kbytes, with an address range from 0000h to 07ffh. the display ram occupies a maximum of 10 kbytes with an address range from 2000h to 47ffh for txt mode and 8000h to 84ffh for cc mode (see fig.14). the two modes although having different address ranges occupy physically the same dram area. 17.3 addressing memory the memory can be addressed by the microcontroller in two ways, either directly using a movx command, or via special function registers depending on what address is required. the dedicated auxiliary ram, and display memory in the range 8000h to 84ffh, can only be accessed using the movx command. the display memory in the range 2000h to 47ffh can either be directly accessed using the movx, or via the special function registers.
2000 feb 23 40 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 17.3.1 txt display memory sfr access the display memory when in txt mode (see fig.15) is configured as 40 columns wide by 25 rows and occupies 1k 8-bit of memory. using txt15.block<3:0>, the required display page can be selected to be written to. the row and column within that block is selected using txt9.r<4:0> and txt10.c<5:0>. the data at the selected position can be read or written using txt11.d<7:0>. whenever a read or write is performed on txt11, the row values stored in txt9 and column value stored in txt10 are automatically incremented. for rows 0 to 24 the column value is incremented up to a maximum of 39, at which point it resets to zero and increments the row counter value. when row 25 column 23 is reached the values of the row and column are both reset to zero. writing values outside of the valid range for txt9 or txt10 will cause undetermined operation of the auto-incrementing function for accesses to txt11. 17.3.2 txt d isplay memory movx access it is important for the generation of osd displays, that use this mode of access, to understand the mapping of the movx address onto the display row and column value. this mapping of row and column onto address is shown in table 12. the values shown are added onto a base address for the required memory block (see fig.14) to give a 16-bit address. table 12 column and row to movx address (lower 10 bits of address) row col.0 ..... col.23 ..... col.31 col.32 ..... col.39 row 0 000h ..... 017h ..... 01fh 3f8h ..... 3ffh row 1 020h ..... 037h ..... 03fh 3f0h ..... 3f7h : ::::: ::: : ::::: ::: row 23 2e0h ..... 3f7h ..... 2ffh 340h ..... 347h row 24 300h ..... 317h ..... 31fh 338h ..... 33fh row 25 320h ..... 337h
2000 feb 23 41 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx handbook, halfpage gsa085 upper 32 kbytes lower 32 kbytes txt block 0 0000h 2000h txt block 9 2400h txt block 1 2800h txt block 2 2c00h txt block 3 3000h txt block 4 3400h txt block 5 3800h txt block 6 3c00h txt block 7 4000h txt block 8 4400h 7fffh cc display 8000h 84ffh ffffh auxiliary 07ffh fig.14 dram memory mapping.
2000 feb 23 42 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.15 txt memory map. handbook, full pagewidth 02030 10 c 9 023 39 column 10 mbk962 control data active position txt9.r < 4:0 > = 01h, txt10.c < 5:0 > = 0ah, txt11 = 43h non-displayable data (byte 10 reserved) row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
2000 feb 23 43 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 17.4 page clearing page clearing is performed on request from either the data capture block, or the microcontroller under the control of the embedded software. at power-on and reset the whole of the page memory is cleared. the txt13.page clearing bit will be set while this takes place. 17.4.1 d ata c apture page clear when a page header is acquired for the first time after a new page request or a page header is acquired with the erase (c4) bit set the page memory is cleared to spaces before the rest of the page arrives. when this occurs, the space code (20h) is written into every location of rows 1 to 23 of the basic page memory, the appropriate packet 27 row of the extension packet memory and the row where teletext packet 24 is written. this last row is either row 24 of the basic page memory, if the txt0.x24 posn bit is set, or row 0 of the extension packet memory, if the bit is not set. page clearing takes place before the end of the tv line in which the header arrived which initiated the page clear. this means that the 1 field gap between the page header and the rest of the page which is necessary for many teletext decoders is not required. 17.4.2 s oftware page clear the software can also initiate a page clear, by setting the txt9.clear memory bit. when it does so, every location in the memory block pointed to by txt15.block<3:0> is cleared to a space code (20h). the clear memory bit is not latched so the software does not have to reset it after it has been set. only one page can be cleared in a tv line so if the software requests a page clear it will be carried out on the next tv line on which the data capture hardware does not force the page to be cleared. a flag, txt13.page clearing, is provided to indicate that a software requested page clear is being carried out. the flag is set when a logic 1 is written into the txt9.clear memory bit and is reset when the page clear has been completed. if txt0.inv on bit = 1 and a page clear is initiated on block 8 all locations are cleared to 00h. 18 data capture the data capture section takes in the analog composite video and blanking signal (cvbs), and from this extracts the required data, which is then decoded and stored in memory. the extraction of the data is performed in the digital domain. the first stage is to convert the analog cvbs signal into a digital form. this is done using an adc sampling at 12 mhz. the data and clock recovery is then performed by a multi-rate video input processor (mulvip). from the recovered data and clock the following data types are extracted wst teletext (625/525), closed caption, vps and wss. the extracted data is stored in either memory (dram) via the memory interface or in sfr locations. 18.1 data capture features two cvbs inputs video signal quality detector data capture for 625-line wst data capture for 525-line wst data capture for us closed caption data capture for vps data (pdc system a) data capture for wide screen signalling (wss) bit decoding automatic selection between 525 wst/625 wst automatic selection between 625 wst/vps on line 16 of vertical blanking interval real-time capture and decoding for wst teletext in hardware, to enable optimized microprocessor throughput up to 10 pages stored on-chip inventory of transmitted teletext pages stored in the transmitted page table (tpt) and subtitle page table (spt) automatic detection of fastext transmission real-time packet 26 engine in hardware for processing accented, g2 and g3 characters signal quality detector for wst/vps data types comprehensive teletext language coverage full field and vertical blanking interval (vbi) data capture of wst data.
2000 feb 23 44 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.16 data capture block diagram. handbook, full pagewidth adc data < 7:0 > vcs sync_filter ttd ttc data slicer and clock recovery output data to memory interface output data to sfrs mbk963 acquisition for wst/vps acquisition for cc/wss cvbs switch cvbs cvbs0 cvbs1 acquisition timing sync separator
2000 feb 23 45 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 18.1.1 cvbs s witch the cvbs switch is used to select the required analog input depending on the value of txt8.cvbs1/ cvbs0. 18.1.2 a nalog - to -d igital c onverter the output of the cvbs switch is passed to a differential-to-single-ended converter (divis), although in this device it is used in single-ended configuration with a reference. the analog output of the divis is converted into a digital representation by a full-flash adc with a sampling rate of 12 mhz. 18.1.3 m ulti - rate video input processor the multi-rate video input processor is a digital signal processor designed to extract the data and recover the clock from a digitized cvbs signal. 18.1.4 d ata standards the data and clock standards that can be recovered are shown in table 13. table 13 data slicing standards 18.1.5 d ata c apture timing the data capture timing section uses the synchronisation information extracted from the cvbs signal to generate the required horizontal and vertical reference timings. the timing section automatically recognizes and selects the appropriate timings for either 625 (50 hz) synchronisation or 525 (60 hz) synchronisation. a flag txt12.video signal quality is set when the timing section is locked correctly to the incoming cvbs signal. when txt12.video signal quality is set another flag txt12.525/ 625 sync can be used to identify the standard. 18.1.6 a cquisition the acquisition sections extracts the relevant information from the serial stream of data from the mulvip and stores it in memory. 18.1.6.1 making a page request a page is requested by writing a series of bytes into the txt3.prd<4:0> sfr which corresponds to the number of the page required. the bytes written into txt3 are stored in a ram with an auto-incrementing address. the start address for the ram is set using the txt2.sc<2:0> to define which part of the page request is being written, and txt2.req<3:0> is used to define which of the 10 page requests is being modified. if txt2.req<3:0> is greater than 09h, then data being written to txt3 is ignored. table 14 shows the contents of the page request ram. up to 10 pages of teletext can be acquired on the 10 page device, when txt1.ext pkt off is set to logic 1, and up to 9 pages can be acquired when this bit is set to logic 0. for a 20 page device the 10 page acquisition channels are banked, the bank being selected using txt2.acq bank. if the do care bit for part of the page number is set logic 0 then that part of the page number is ignored when the teletext decoder is deciding whether a page being received off air should be stored or not. for example, if the do care bits for the four subcode digits are all set to logic 0 then every subcode version of the page will be captured. table 14 the contents of the page request ram data standard clock rate 625 wst 6.9375 mhz 525 wst 5.7272 mhz vps 5.0 mhz wss 5.0 mhz closed caption 500 khz start column prd4 prd3 prd2 prd1 prd0 0 do care magazine hold mag2 mag1 mag0 1 do care page tens pt3 pt2 pt1 pt0 2 do care page units pu3 pu2 pu1 pu0 3 do care hour tens x x ht1 ht0 4 do care hours units hu3 hu2 hu1 hu0 5 do care minutes tens x mt2 mt1 mt0 6 do care minutes units mu3 mu2 mu1 mu0 7x xxe1e0
2000 feb 23 46 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx when the hold bit is set to a logic 0 the teletext decoder will not recognise any page as having the correct page number and no pages will be captured. in addition to providing the user requested hold function this bit should be used to prevent the inadvertent capture of an unwanted page when a new page request is being made. for example, if the previous page request was for page 100 and this was being changed to page 234, it would be possible to capture page 200 if this arrived after only the requested magazine number had been changed. the e1 and e0 bits control the error checking which should be carried out on packets 1 to 23 when the page being requested is captured. this is described in more detail in section 18.1.6.3. for a multi-page device, each packet can only be written into one place in the teletext ram so if a page matches more than one of the page requests the data is written into the area of memory corresponding to the lowest numbered matching page request. at power-up each page request defaults to any page, hold on and error check mode 0. 18.1.6.2 rolling headers and time when a new page has been requested it is conventional for the decoder to turn the header row of the display green and to display each page header as it arrives until the correct page has been found. when a page request is changed (i.e. when the txt3 sfr is written to) a flag (pblf) is written into bit 5, column 9, row 25 of the corresponding block of the page memory. the state of the flag for each block is updated every tv line, if it is set for the current display block, the acquisition section writes all valid page headers which arrive into the display block and automatically writes an alphanumeric green character into column 7 of row 0 of the display block every tv line. when a requested page header is acquired for the first time, rows 1 to 23 of the relevant memory block are cleared to space, i.e. have 20h written into every column, before the rest of the page arrives. row 24 is also cleared if the txt0.x24 posn bit is set. if the txt1.ext pkt off bit is set the extension packets corresponding to the page are also cleared. the last 8 characters of the page header are used to provide a time display and are always extracted from every valid page header as it arrives and written into the display block. the txt0.disable header roll bit prevents any data being written into row 0 of the page memory except when a page is acquired off air i.e. rolling headers and time are not written into the memory. the txt1.acq off bit prevents any data being written into the memory by the teletext acquisition section. when a parallel magazine mode transmission is being received only headers in the magazine of the page requested are considered valid for the purposes of rolling headers and time. only one magazine is used even if dont care magazine is requested. when a serial magazine mode transmission is being received all page headers are considered to be valid. 18.1.6.3 error checking before teletext packets are written into the page memory they are error checked. the error checking carried out depends on the packet number, the byte number, the error check mode bits in the page request data and the txt1.8-bit bit. if an uncorrectable error occurs in one of the hamming checked addressing and control bytes in the page header or in the hamming checked bytes in packet 8/30, bit 4 of the byte written into the memory is set, to act as an error flag to the software. if uncorrectable errors are detected in any other hamming checked data the byte is not written into the memory.
2000 feb 23 47 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.17 error checking. handbook, full pagewidth mgk465 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 0 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 1 packet x/0 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 0, error check mode = 0 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 0, error check mode = 1 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 0, error check mode = 2 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 0, error check mode = 3 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 1 packet x/1-23 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 0 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 '8-bit' bit = 1 packet x/24 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 packet x/27/0 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 packet 8/30/0,1 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8-bit data packet 8/30/2,3,4-15 odd parity checked 8/4 hamming checked
2000 feb 23 48 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.18 packet storage locations. (1) if x24 posn bit = 1. (2) vps data block 9, unused in blocks 0 to 8. (3) byte 10 reserved. handbook, full pagewidth row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0678 9 023 39 packet x/0 basic page blocks (0 to 8/9) osd only packet x/1 packet x/2 packet x/3 packet x/4 packet x/5 packet x/6 packet x/7 packet x/8 packet x/9 packet x/10 packet x/11 packet x/12 packet x/13 packet x/14 packet x/15 packet x/16 packet x/17 packet x/18 packet x/19 packet x/20 packet x/21 packet x/22 packet x/23 packet x/24 (1) gsa003 control data vps data (2) 10 (3)
2000 feb 23 49 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 18.1.6.4 teletext memory organisation the teletext memory is divided into 2 banks of 10 blocks. normally, when the txt1.ext pkt off bit is logic 0, each of blocks 0 to 8 contains a teletext page arranged in the same way as the basic page memory of the page device and block 9 contains extension packets. when the txt1.ext pkt off bit is logic 1, no extension packets are captured and block 9 of the memory is used to store another page. the number of the memory block into which a page is written corresponds to the page request number which resulted in the capture of the page. packet 0, the page header, is split into two parts when it is written into the text memory. the first 8 bytes of the header contain control and addressing information. they are hamming decoded and written into columns 0 to 7 of row 25. row 25 also contains the magazine number of the acquired page and the plbf flag but the last 14 bytes are unused and may be used by the software, if necessary. fig.19 extension packet storage locations. (1) if x24 posn bit = 0. (2) byte 10 reserved. handbook, full pagewidth gsa002 0 1 2 3 4 5 6 7 8 9 923 0 10 11 12 13 14 15 20 21 22 23 24 25 16 17 18 19 row packet x/24 for page in block 0 (1) packet x/24 for page in block 1 (1) packet x/27/0 for page in block 0 packet x/27/0 for page in block 1 packet x/24 for page in block 2 (1) packet x/27/0 for page in block 2 packet x/24 for page in block 3 (1) packet x/27/0 for page in block 3 packet x/24 for page in block 4 (1) packet x/27/0 for page in block 4 packet x/24 for page in block 5 (1) packet x/27/0 for page in block 5 packet x/24 for page in block 6 (1) packet x/27/0 for page in block 6 packet x/24 for page in block 7 (1) packet x/27/0 for page in block 7 packet x/24 for page in block 8 (1) packet x/27/0 for page in block 8 packet 8/30/0.1 packet 8/30/2.3 packet 8/30/4-15 vps data extension packet block (9) 10 (2)
2000 feb 23 50 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 18.1.6.5 row 25 data contents the hamming error flags are set if the on-board 8/4 hamming checker detects that there has been an uncorrectable (2-bit) error in the associated byte. it is possible for the page to still be acquired if some of the page address information contains uncorrectable errors if that part of the page request was a dont care. there is no error flag for the magazine number as an uncorrectable error in this information prevents the page being acquired. the interrupt sequence (c9) bit is automatically dealt with by the acquisition section so that rolling headers do not contain a discontinuity in the page number sequence. the magazine serial (c11) bit indicates whether the transmission is a serial or a parallel magazine transmission. this affects the way the acquisition section operates and is dealt with automatically. the newsflash (c5), subtitle (c6), suppress header (c7), inhibit display (c10) and language control (c12 to 14) bits are dealt with automatically by the display section. the update (c8) bit has no effect on the hardware. the remaining 32 bytes of the page header are parity checked and written into columns 8 to 39 of row 0. bytes which pass the parity check have the msb set to a logic 0 and are written into page memory. bytes with parity errors are not written into the memory. table 15 the data in row 25 of the basic page memory col bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000 hamming error pu3 pu2 pu1 pu0 1000 hamming error pt3 pt2 pt1 pt0 2000 hamming error mu3 mu2 mu1 mu0 3000 hamming error c4 mt2 mt1 mt0 4000 hamming error hu3 hu2 hu1 hu0 5000 hamming error c6 c5 ht1 ht0 6000 hamming error c10 c9 c8 c7 7000 hamming error c14 c13 c12 c11 8000 found 0 mag2 mag1 mag0 9 0 0 pblf 0 0000 10 to 23 --- unused ----
2000 feb 23 51 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 18.1.6.6 inventory page if the txt0.inv on bit is a logic 1, memory block 8 is used as an inventory page.the inventory page consists of two tables: the transmitted page table (tpt) and the subtitle page table (spt). in each table, every possible combination of the page tens and units digit, 00h to ffh, is represented by a byte. each bit of these bytes corresponds to a magazine number so each page number, from 100h to 8ffh, is represented by a bit in the table. the bit for a particular page in the tpt is set when a page header is received for that page. the bit in the spt is set when a page header for the page is received which has the subtitle page header control bit (c6) set. the bit for a particular page in the tpt is set when a page header is received for that page. the bit in the spt is set when a page header for the page is received which has the subtitle page header control bit (c6) set. fig.20 transmitted/subtitle page organisation. handbook, full pagewidth x00 x01 x02 x03 x04 x05 x06 x07 x08 x09 x0a x0b x0c x0d x0e x0f x10 x11 x12 x13 x14 x15 x16 x17 x18 x19 x1a x1b x1c x1d x1e x1f x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x2a x2b x2c x2d x2e x2f x30 x31 x32 x33 x34 x35 x36 x37 x38 x39 x3a x3b x3c x3d x3e x3f xc0 xc1 xc2 xc3 xc4 xc5 xc6 xc7 xc8 xc9 xca xcb xcc xcd xce xcf xd0 xd1 xd2 xd3 xd4 xd5 xd6 xd7 xd8 xd9 xda xdb xdc xdd xde xdf xe0 xe1 xe2 xe3 xe4 xe5 xe6 xe7 xe8 xe9 xea xeb xec xed xee xfef xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xfa xfb xfc xfd xfe xff 7xx bit 7 bytes in the table bits in each byte column row n n + 1 n + 6 n + 7 0 0 mgd160 81624 3239 6xx 5xx 4xx 3xx 2xx 1xx 8xx
2000 feb 23 52 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.21 inventory page organisation. handbook, full pagewidth mgd165 0 1 2 3 4 5 6 7 8 9 23 0 039 10 11 12 13 14 15 20 21 22 23 24 25 16 17 18 19 row unused unused unused unused unused unused unused unused unused transmitted pages table subtitle pages table
2000 feb 23 53 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 18.1.6.7 packet 26 processing one of the uses of packet 26 is to transmit characters which are not in the basic teletext character set. the family automatically decodes packet 26 data and, if a character corresponding to that being transmitted is available in the character set, automatically writes the appropriate character code into the correct location in the teletext memory. this is not a full implementation of the packet 26 specification allowed for in level 2 teletext, and so is often referred to as level 1.5. by convention, the packets 26 for a page are transmitted before the normal packets. to prevent the default character data overwriting the packet 26 data the device incorporates a mechanism which prevents packet 26 data from being overwritten. the mechanism is disabled when the spanish national option is detected as the spanish transmission system sends even parity (i.e. incorrect) characters in the basic page locations corresponding to the characters sent via packet 26 and these will not overwrite the packet 26 characters anyway. the special treatment of spanish national option is prevented if txt12.rom ver r4 is logic 0 or if the txt8.disable spanish is set. packet 26 data is processed regardless of the txt1.ext pkt off bit, but setting thetxt1.x26 off disables packet 26 processing. the txt8.pkt26 received bit is set by the hardware whenever a character is written into the page memory by the packet 26 decoding hardware. the flag can be reset by writing a logic 0 into the sfr bit. 18.1.6.8 525-line world system teletext the 525-line format is similar to the 625-line format but the data rate is lower and there are less data bytes per packet (32 rather than 40). there are still 40 characters per display row so extra packets are sent each of which contains the last 8 characters for four rows. these packets can be identified by looking at the tabulation bit (t), which replaces one of the magazine bits in 525-line teletext. when an ordinary packet with t = 1 is received, the decoder puts the data into the four rows starting with that corresponding to the packet number, but with the 2 lsbs set to logic 0. for example, a packet 9 with t = 1 (packet x/1/9) contains data for rows 8, 9, 10 and 11. the error checking carried out on data from packets with t = 1 depends on the setting of the txt1. 8-bit bit and the error checking control bits in the page request data and is the same as that applied to the data written into the same memory location in the 625-line format. the rolling time display (the last 8 characters in row 0) is taken from any packets x/1/1, 2 or 3 received. in parallel magazine mode only packets in the correct magazine are used for rolling time. packet number x/1/0 is ignored. the tabulation bit is also used with extension packets. the first 8 data bytes of packet x/1/24 are used to extend the fastext prompt row to 40 characters. these characters are written into whichever part of the memory the packet 24 is being written into (determined by the x24 posn bit). packets x/0/27/0 contain 5 fastext page links and the link control byte and are captured, hamming checked and stored in the same way as are packets x/27/0 in 625-line text. packets x/1/27/0 are not captured. because there are only 2 magazine bits in 525-line text, packets with the magazine bits all set to a logic 0 are referred to as being in magazine 4. therefore, the broadcast service data packet is packet 4/30, rather than packet 8/30. as in 625-line text, the first 20 bytes of packet 4/30 contain encoded data which is decoded in the same way as that in packet 8/30. the last 12 bytes of the packet contains half of the parity encoded status message. packet 4/0/30 contains the first half of the message and packet 4/1/30 contains the second half. the last 4 bytes of the message are not written into memory. the first 20 bytes of the each version of the packet are the same so they are stored whenever either version of the packet is acquired. in 525-line text each packet 26 only contains ten 24/18 hamming encoded data triplets, rather than the 13 found in 625-line text. the tabulation bit is used as an extra bit (the msb) of the designation code, allowing 32 packet 26s to be transmitted for each page. the last byte of each packet 26 is ignored.
2000 feb 23 54 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.22 packet storage locations, 525-line. (1) if x24 posn bit = 1. (2) byte 10 reserved. handbook, full pagewidth gsa004 row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0678 9 023 39 packet x/0/0 osd only rolling time aw/ag packet x/0/1 packet x/1/1 packet x/0/2 packet x/0/3 packet x/0/4 packet x/1/4 packet x/0/5 packet x/0/6 packet x/0/7 packet x/0/8 packet x/1/8 packet x/0/9 packet x/0/10 packet x/0/11 packet x/0/12 packet x/1/12 packet x/0/13 packet x/0/14 packet x/0/15 packet x/0/16 packet x/1/16 packet x/0/17 packet x/0/18 packet x/0/19 packet x/0/20 packet x/1/20 packet x/0/21 packet x/0/22 packet x/0/23 packet x/0/24 (1) packet x/1 /24 (1) control data 10 (2)
2000 feb 23 55 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 18.1.6.9 fastext detection when a packet 27, designation code 0 is detected, whether or not it is acquired, the txt13.fastext bit is set. if the device is receiving 525-line teletext, a packet x/0/27/0 is required to set the flag. the flag can be reset by writing a logic 0 into the sfr bit. when a packet 8/30 is detected, or a packet 4/30 when the device is receiving a 525-line transmission, the txt13.pkt 8/30 is set. the flag can be reset by writing a logic 0 into the sfr bit. 18.1.6.10 broadcast service data detection when a packet 8/30 is detected, or a packet 4/30 when the device is receiving a 525-line transmission, the txt13. pkt 8/30 flag is set. the flag can be reset by writing a logic 0 into the sfr bit. 18.1.6.11 vps acquisition when the txt0.vps on bit is set, any vps data present on line 16, field 0 of the cvbs signal at the input of the teletext decoder is error checked and stored in row 25, block 9 of the basic page memory. the device automatically detects whether teletext or vps is being transmitted on this line and decodes the data appropriately. each vps byte in the memory consists of 4 biphase decoded data bits (bits 0 to 3), a biphase error flag (bit 4) and three logic 0s (bits 5 to 7). the most significant bit of the vps data cannot be set to logic 1. the txt13.vps received bit is set by the hardware whenever vps data is acquired. full details of the vps system can be found in the specification domestic video program delivery control system (pdc); ebu tech. 3262-e. 18.1.7 wst acquisition the family is capable of acquiring level 1.5 625-line and 525-line world system teletext. 18.1.8 wss acquisition the wide screen signalling data transmitted on line 23 gives information on the aspect ratio and display position of the transmitted picture, the position of subtitles and on the camera/film mode. some additional bits are reserved for future use. a total of 14 data bits are transmitted. all of the available data bits transmitted by the wide screen signalling signal are captured and stored in sfrs wss1, wss2 and wss3. the bits are stored as groups of related bits and an error flag is provided for each group to indicate when a transmission error has been detected in one or more of the bits in the group. wide screen signalling data is only acquired when the txt8.wss on bit is set. the txt8.wss received bit is set by the hardware whenever wide screen signalling data is acquired. the flag can be reset by writing a logic 0 into the sfr bit. fig.23 vps data storage. handbook, full pagewidth teletext page header data vps byte 11 row 25 10 11 column 0 9 mbk964 vps byte 12 vps byte 13 vps byte 14 vps byte 15 vps byte 4 vps byte 5 12 13 14 15 16 17 18 19 20 21 22 23
2000 feb 23 56 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 18.1.9 c losed c aption acquisition the us closed caption data is transmitted on line 21 (525-line timings) and is used for captioning information, text information and extended data services. full details can be found in the document recommended practise for line 21 data service eia-608 . closed caption data is only acquired when txt21.cc on bit is set. two bytes of data are stored per field in sfrs the first bye is stored in ccdat1 and the second byte is stored in ccdat2. the value in the ccdat registers are reset to 00h at the start of the closed caption line defined by cclin.cs<4:0>. at the end of the closed caption line an interrupt is generated if ie.ecc is active. the processing of the closed caption data to convert into a displayable format is performed by software. 19 display the display section is based on the requirements for a level 1.5 wst teletext and us closed caption. there are some enhancements for use with locally generated on-screen displays. the display section reads the contents of the display memory and interprets the control/character codes. from this information and other global settings, the display produces the required rgb signals and video/data (fast blanking) signal for a tv signal processing device. the display is synchronized to the tv signal processing device by way of horizontal and vertical sync signals provided by external circuits (slave sync mode). from these signals all display timings are derived. 19.1 display features teletext and enhanced osd modes level 1.5 wst features us closed caption features serial and parallel display attributes single/double/quadruple width and height for characters scrolling of display region variable flash rate controlled by software globally selectable scan lines per row 9/10/13/16 globally selectable character matrix (h v) 12 9, 12 10, 12 13 or 12 16 italics soft colours using clut with 4096 colour palette underline overline fringing (shadow) selectable from n-s-e-w direction fringe colour selectable meshing of defined area contrast reduction of defined area cursor special graphics characters with two planes, allowing four colours per character 32 software redefinable on-screen display characters 4 wst character sets (g0/g2) in single device (e.g. latin, cyrillic, greek and arabic) g1 mosaic graphics, limited g3 line drawing characters wst character sets and closed caption character set in single device.
2000 feb 23 57 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.24 display block diagram. handbook, full pagewidth microprocessor interface display timing hsync clk vsync character font addressing address address data data address address data data address data control to memory interface from memory interface function registers parallel/serial converter and fringing attribute handling clut ram display data addressing mbk965 character rom and drcs data buffer dac dac dac gbfb r
2000 feb 23 58 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.2 display modes the display section has two distinct modes with different features available in each. the two modes are: txt: this is the display configured as the wst mode with additional serial and global attributes. the display is configured as a fixed 25 rows with 40 characters per row. cc: this is the display configured as the us closed caption mode. the display is configured as a maximum of 16 rows with a maximum of 48 characters per row. in both of the above modes the character matrix, and tv lines per row can be defined. there is an option of 9, 10, 13 and 16 tv lines per display row, and a character matrix (h v) of 12 9, 12 10, 12 13, or 12 16. not all combinations of tv lines per row and maximum display rows give a sensible osd display, since there is a limited number of tv scan lines available. special function register txt21 and memory mapped registers are used to control the mode selection. throughout the section the features will be described and their function in each of the modes given. if the feature is different in either mode then this is stated. 19.2.1 f eatures available in each mode table 16 shows a list of features available in each mode, and also if the setting is a serial/parallel attribute, or has a global effect on all the display. table 16 display features feature txt cc flash serial serial boxes txt/osd (serial) serial horizontal size x1, x2 or x4 (serial) x1 or x2 (serial) vertical size x1 or x2 (serial); x4 (global) x1 or x2 (serial) italic n/a serial foreground colours 8 (serial) 8 + 8 (parallel) background colours 8 (serial) 16 (serial) soft colours (clut) 16 from 4096 16 from 4096 underline n/a serial overline n/a serial fringe n + s+e+w n+s+e+w fringe colour 16 (global) 16 (serial) meshing of background black or colour (global) all (global) fast blanking polarity yes yes screen colour 16 (global) 16 (global) drcs 32 (global) 32 (global) character matrix (h v) 12 9, 12 10, 12 13 or 12 16 12 9, 12 10, 12 13 or 12 16 number of rows 25 16 number of columns 40 48 number of characters displayable 1000 768 cursor yes yes special graphics (2 planes per character) 16 16 scroll no yes
2000 feb 23 59 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.3 display feature descriptions all display features are now described in detail for both txt and cc modes. 19.3.1 f lash flashing causes the foreground colour pixel to be displayed as the background pixels. the flash frequency is controlled by software setting and resetting the mmr status (see table 34) at the appropriate interval. cc: this attribute is valid from the time set (see table 22) until the end of the row or until otherwise modified. txt: this attribute is set by the control character flash (08h) (see fig.30) and remains valid until the end of the row or until reset by the control character steady (09h). 19.3.2 b oxes cc: this attribute is valid from the time set until end of row or otherwise modified if set with serial mode 0. if set with serial mode 1, then it is set from the next character onwards. in text mode (within cc mode) the background colour is displayed regardless of the setting of the box attribute bit. boxes take effect only during mixed mode, where boxes are set in this mode the background colour is displayed. character locations where boxes are not set show video/screen colour (depending on the setting in the mmr display control) in stead of the background colour. txt: two types of boxes exist the teletext box and the osd box. the teletext box is activated by the start box control character (0bh). two start box characters are required to begin a teletext box, with the box starting between the 2 characters. the box ends at the end of the line or after a end box control character. txt mode can also use osd boxes, they are started using size implying osd control characters (bch/bdh/beh/bfh). the box starts after the control character (set after) and ends either at the end of the row or at the next size implying osd character (set at). the attributes flash, teletext box, conceal, separate graphics, twist and hold graphics are all reset at the start of an osd box, as they are at the start of the row. osd boxes are only valid in tv mode which is defined by txt5 = 03h and txt6 = 03h. 19.3.3 s ize the size of the characters can be modified in both the horizontal and vertical directions. cc: two sizes are available in both the horizontal and vertical directions. the sizes available are normal ( 1), double ( 2) height/width and any combination of these. the attribute setting is always valid for the whole row. mixing of sizes within a row is not possible. txt: three horizontal sizes are available normal ( 1), double ( 2) and quadruple ( 4). the control characters normal size (0ch/bch) enables normal size, the double width or double size (0eh/beh/0fh/bfh) enables double width characters. any two consecutive combination of double width or double size (0eh/beh/0fh/bfh) activates quadruple width characters, provided quadruple width characters are enabled by txt4.quad width enable. three vertical sizes are available normal(x1), double (x2) and quadruple (x4). the control characters normal size (0ch/bch) enable normal size, the double height or double size (0dh/bdh/0fh/bfh) enable double height characters. quadruple height character are achieved by using double height characters and setting the global attributes txt7.double height (expand) and txt7.bottom/ top. if double height characters are used in teletext mode, single height characters in the lower row of the double height character are automatically disabled. 19.3.4 i talic cc: this attribute is valid from the time set until the end of the row or otherwise modified. the attribute causes the character foreground pixels to be offset horizontally by 1 pixel per 4 scan lines (interlaced mode). the base is the bottom left character matrix pixel. the pattern of the character is indented as shown in fig.25. txt: the italic attribute is not available.
2000 feb 23 60 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.25 italic characters. handbook, full pagewidth 0 0 1 3 5 7 8 9 10 field 1 12 16 character matrix 12 13 character matrix indented by 7/6/4 indented by 6/5/3 indented by 5/4/2 indented by 4/3/1 indented by 3/2/0 indented by 2/1 indented by 1/0 mbk970 field 2 11 12 13 14 15 2 2 4 4 6 6 810 0 2 4 6 810 indented by 0 02468100246810 12 10 character matrix 02468100246810 19.3.5 c olours a colour look-up table (clut) with 16 colour entries is provided. the colours are programmable out of a palette of 4096 (4 bits per r, g and b). the clut is defined by writing data to a ram that resides in the movx address space of the 80c51. table 17 clut colour values 19.3.6 f oreground c olour cc: the foreground colour can be chosen from 8 colours on a character by character basis. two sets of 8 colours are provided. a serial attribute switches between the banks (see table 22 serial mode 1, bit 7). the colours are the clut entries 0 to 7 or 8 to 15. txt: the foreground colour is selected via a control character (see fig.29). the colour control characters takes effect at the start of the next character (set-after) and remain valid until the end of the row, or until modified by a control character. only 8 foreground colours are available. the text foreground control characters map to the clut entries as shown in table 18. red<3:0> (b11 to b8) green<3:0 > (b7 to b4) blue<3:0> (b3 to b0) colour entry 0000 0000 0000 0 0000 0000 1111 1 ... ... ... ... 1111 1111 0000 14 1111 1111 1111 15
2000 feb 23 61 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx table 18 foreground clut mapping 19.3.7 b ackground colour cc: this attribute is valid from the time set until end of row or otherwise modified if set with serial mode 0. if set with serial mode 1, then the colour is set from the next character onwards. the background colour can be chosen from all 16 clut entries. txt: the control character new background (1dh) is used to change the background colour to the current foreground colour. the selection is immediate (set at) and remains valid until the end of the row or until otherwise modified. the text background control characters map to the clut entries as shown in table 19: table 19 background clut mapping 19.3.8 b ackground duration the attribute when set takes effect from the current position until the end of the text display defined in the mmr text area end. cc: the background duration attribute (see table 22, serial mode 1, bit 8) in combination with the end of row attribute (see table 22, serial mode 1, bit 9) forces the background colour to be display on the row until the end of the text area is reached. txt: this attribute is not available. 19.3.9 u nderline the underline attribute causes the characters to have the bottom scan line of the character cell forced to foreground colour, including spaces. if background duration is set, then underline is set until the end of the text area. cc: the underline attribute (see table 22, serial mode 0/1, bit 4) is valid from the time set until end of row or otherwise modified. txt: this attribute is not available. 19.3.10 o verline the overline attribute causes the characters to have the top scan line of the character cell forced to foreground colour, including spaces. if background duration is set, then overline is set until the end of the text area. cc: the overline attribute (see table 22, serial mode 0/1, bit 5) is valid from the time set until end of row or otherwise modified. overlining of italic characters is not possible. txt: this attribute is not available. 19.3.11 e nd of r ow cc: the number of characters in a row is flexible and can determined by the end of row attribute (see table 22 serial mode 1, bit 9). however the maximum number of character positions displayed is determined by the setting of the mmr text position horizontal and mmr text area end. note that when using the end of row attribute the next character location after the attribute should always be occupied by a space. txt: this attribute is not available, row length is fixed at 40 characters. control code defined colour clut entry 00h black 0 01h red 1 02h green 2 03h yellow 3 04h blue 4 05h magenta 5 06h cyan 6 07h white 7 control code defined colour clut entry 00h + 1dh black 8 01h + 1dh red 9 02h + 1dh green 10 03h + 1dh yellow 11 04h + 1dh blue 12 05h + 1dh magenta 13 06h + 1dh cyan 14 07h + 1dh white 15
2000 feb 23 62 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.3.12 f ringing a fringe (shadow) can be defined around characters. the fringe direction is individually selectable in any of the north, south, east and west direction using the mmr fringing control. the colour of the fringe can also be defined as one of the entries in the clut, again using mmr fringing control. cc: the fringe attribute (see table 22, serial mode 0, bit 9) is valid from the time set until the end of the row or otherwise modified. txt: the display of fringing in txt mode is controlled by the txt4.shadow enable bit. when set all the alphanumeric characters being displayed are shadowed, graphics characters are not shadowed. 19.3.13 m eshing the attribute effects the background colour being displayed. alternate pixels are displayed as the background colour or video. the structure is offset by 1 pixel from scan line to scan line, thus achieving a checker board display of the background colour and video. cc: the setting of the msh bit in mmr display control has the effect of meshing any background colour. txt: there are two meshing attributes one that only affects black background colours txt4.b mesh enable and a second that only affects backgrounds other than black txt4.c mesh enable. a black background is defined as clut entry 8, a non-black background is defined as clut entry 9 to 15. fig.26 south and south-west fringing. handbook, full pagewidth mbk972 handbook, full pagewidth mbk973 fig.27 meshing and meshing/fringing (south + west).
2000 feb 23 63 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.3.14 c ursor the cursor operates by reversing the background and foreground colours in the character position pointed to by the active cursor position. the cursor is enabled using txt7.cursor on. when active, the row the cursor appears on is defined by txt9.r<4:0> and the column is defined by txt10.c<5:0>. the position of the cursor can be fixed using txt9.cursor freeze. cc: the valid range for row is 0 to 15. the valid range for column is 0 to 47. the cursor remains rectangular at all times, its shape is not affected by italic attribute, therefore it is not advised to use the cursor with italic characters. txt: the valid range for row positioning is 0 to 24. the valid range for column is 0 to 39. 19.3.15 s pecial graphics characters cc/txt: several special characters are provided for improved osd effects. these characters provide a choice of 4 colours within a character cell. the total number of special graphics characters is limited to 16. they are stored in the character codes 8xh and 9xh of the character table (32 rom characters), or in the drcs which overlay character codes 8xh and 9xh. each special graphics character uses two consecutive normal characters. fringing, underline and overline is not possible for special graphics characters. special graphics characters are activated when txt20.osd planes = 1. if the screen colour is transparent (implicit in mixed mode) and inside the object the box attribute is set, then the object is surrounded by video. if the box attribute is not set the background colour inside the object will also be displayed as transparent. table 20 special character colour allocation plane 1 plane 0 colour allocation 0 0 background colour 0 1 foreground colour 1 0 clut entry 6 1 1 clut entry 7 fig.28 cursor display. handbook, full pagewidth mbk971 ab c def fig.29 special character example. this example could also be done with 8 special characters. handbook, full pagewidth mgk550 volume background colour "set at" (mode 0) background colour "set after" (mode 1) serial attribute foreground colour 7 background colour special character foreground colour normal character foreground colour 6
2000 feb 23 64 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.4 character and attribute coding this section describes the character and attribute coding for each mode. 19.4.1 cc mode character coding is split into character oriented attributes (parallel) and character group coding (serial). the serial attributes take effect either at the position of the attribute (set at), or at the following location (set after) and remain effective until either modified by a new serial attribute or until the end of the row. a serial attribute is represented as a space (the space character itself however is not used for this purpose), the attributes that are still active, e.g. overline and underline will be visible during the display of the space. the default setting at the start of a row is: 1 size flash off overline off underline off italics off display mode = superimpose fringing off background colour duration = 0 end of row = 0. the coding is done in 12-bit words. the codes are stored sequentially in the display memory. a maximum of 768 character positions can be defined for a single display. 19.4.2 txt mode character coding is in a serial format, with only one attribute being changed at any single location. the serial attributes take effect either at the position of the attribute (set at), or at the following location (set after). the attribute remains effective until either modified by new serial attributes or until the end of the row. the default settings at the start of a row are: foreground colour white (clut address 7) background colour black (clut address 8) horizontal size 1, vertical size 1 (normal size) alphanumeric on contiguous mosaic graphics release mosaics flash off box off conceal off twist off. the attributes have individual codes which are defined in the basic character table (see fig.30). 19.4.3 p arallel character coding table 21 parallel character coding bits description 0 to 7 8-bit character code 8 to 10 3 bits for 8 foreground colours 11 mode bit: 0 = parallel code
2000 feb 23 65 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.4.4 s erial character coding table 22 serial character coding bits description serial mode 0 (set at) serial mode 1 char.pos. 1 (set at) char.pos. >1 (set after) 0 to 3 4 bits for 16 background colours 4 bits for 16 background colours 4 bits for 16 background colours 4 underline switch: horizontal size: underline switch: 0 = underline off 0 = normal 0 = underline off 1 = underline on 1 = 2 1 = underline on 5 overline switch: vertical size: overline switch: 0 = overline off 0 = normal 0 = overline off 1 = overline on 1 = 2 1 = overline on 6 display mode: display mode: display mode: 0 = superimpose 0 = superimpose 0 = superimpose 1 = boxing 1 = boxing 1 = boxing 7 flash switch: foreground colour switch foreground colour switch 0 = ?ash off 0 = bank 0 (colours 0 to 7) 0 = bank 0 (colours 0 to 7) 1 = ?ash on 1 = bank 1 (colours 8 to 15) 1 = bank 1 (colours 8 to 15) 8 italic switch: background colour duration: background colour duration (set at): 0 = italics off 0 = stop bgc 0 = stop bgc 1 = italics on 1 = set bgc to end of row 1 = set bgc to end of row 9 fringing switch: end of row end of row (set at): 0 = fringing off 0 = continue row 0 = continue row 1 = fringing on 1 = end row 1 = end row 10 switch for serial coding: switch for serial coding: switch for serial coding: 0 = mode 0 1 = mode 1 0 = mode 0 1 = mode 1 0 = mode 0 1 = mode 1 11 mode bit: mode bit: mode bit: 1 = serial code 1 = serial code 1 = serial code
2000 feb 23 66 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth mbk974 normal height b 3 b 2 b 1 b 0 b 4 b 5 b 6 b 7 0 1 2 2a 3 3a 4 5 6 6a 7 7a 8 8a 9a 9c column r o w b i t s 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 a 1 0 1 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 1 1 1 e 1 1 1 0 double width hold graphics f 1 1 1 1 double size release graphics b 1 0 1 1 start box twist c 1 1 0 0 black back - ground d 1 1 0 1 double height new back - ground a 1 0 1 0 end box separated graphics 9 1 0 0 1 steady contiguous graphics 8 1 0 0 0 flash conceal display 7 0 1 1 1 alpha white graphics white 6 0 1 1 0 alpha cyan graphics cyan 5 0 1 0 1 alpha magenta graphics magenta 4 0 1 0 0 alpha blue graphics blue 3 0 0 1 1 alpha yellow graphics yellow 2 0 0 1 0 alpha green graphics green 0 0 0 0 0 alpha black graphics black 1 0 0 0 1 alpha red graphics red b 1 0 1 1 def 1 1 0 1 1 1 1 0 1 1 1 1 def 1 1 0 1 1 1 1 0 1 1 1 1 double width osd double size osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd e/w = 0 e/w = 1 osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt normal size osd double height osd back- ground white back- ground cyan back- ground magenta back- ground blue back- ground yellow back- ground green back- ground black back ground red osd character dependent on the language of page, refer to national option characters customer definable on-screen display character fig.30 txt basic character set (pan-european).
2000 feb 23 67 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.5 screen and global controls a number of attributes are available that affect the whole display region, and cannot be applied selectively to regions of the display. 19.5.1 tv scan lines per row the number of tv scan lines per field used for each display row can be defined, the value is independent of the character size being used. the number of lines can be either 10, 13 or 16 per display row. the number of tv scan lines per row is defined txt21.disp lines<1:0>. a value of 9 lines per row can be achieved if the display is forced into 525-line display mode by txt17.force disp<1:0>, or if the device is in 10 line mode and the automatic detection circuitry within display finds 525-line display syncs. 19.5.2 c haracter matrix (h v) there are three different character matrices available, these are 12 10, 12 13 and 12 16. the selection is made using txt21.char size<1:0> and is independent of the number of display lines per row. if the character matrix is less than the number of tv scan lines per row then the matrix is padded with blank lines. if the character matrix is greater than the number of tv scan lines then the character is truncated. 19.5.3 d isplay modes cc: when attributes superimpose or boxing (see table 22, serial mode 0/1, bit 6) are set, the resulting display depends on the setting of the following screen control mode bits in the mmr display control. txt: the display mode is controlled by the bits in the txt5 and txt6. there are 3 control functions - text on, background on and picture on. separate sets of bits are used inside and outside teletext boxes so that different display modes can be invoked. txt6 is used if the newsflash (c5) or subtitle (c6) bits in row 25 of the basic page memory are set otherwise txt5 is used. this allows the software to set up the type of display required on newsflash and subtitle pages (e.g. text inside boxes, tv picture outside) this will be invoked without any further software intervention when such a page is acquired. when teletext box control characters are present in the display page memory, the appropriate box control bit must be set, txt7.box on 0, txt7.box on 1 - 23 or txt7.box on 24. this allows the display mode to be different inside the teletext box compared to outside. these bits are present to allow boxes in certain areas of the screen to be disabled. the use of teletext boxes for osd messages has been superseded in this device by the osd box concept, but these bits remain to allow teletext boxes to be used, if required. table 23 selection of display modes table 24 txt display control bits mod1 mod0 display mode description 0 0 video disables all display activities, sets the rgb to true black and vds to video. 0 1 full text displays screen colour at all locations not covered by character foreground or background colour. the box attribute has no effect. 1 0 mixed screen colour displays screen colour at all locations not covered by character foreground, within boxed areas or, background colour. 1 1 mixed video displays video at all locations not covered by character foreground, within boxed areas or, background colour. picture on text on background on effect 0 0 x text mode, black screen 0 1 0 text mode, background always black 0 1 1 text mode 1 0 x video mode 1 1 0 mixed text and tv mode 1 1 1 text mode, tv picture outside text area
2000 feb 23 68 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.6 screen colour screen colour is displayed from 10.5 to 62.5 ms after the active edge of the hsync input and on tv lines 23 to 310 inclusive, for a 625-line display, and lines 17 to 260 inclusive for a 525-line display. cc: the screen colour is defined by the mmr display control and points to a location in the clut table. the screen colour covers the full video width. it is visible when the full text or mixed screen colour mode is set and no foreground or background pixels are being displayed. txt: the register bits txt17.screen col<2:0> can be used to define a colour to be displayed in place of tv picture and the black background colour. if the bits are all set to zero, the screen colour is defined as transparent and tv picture and background colour are displayed as normal. otherwise the bits define clut entries 9 to 15. 19.7 text display controls 19.7.1 t ext display configuration (cc mode ) two types of areas are possible. the one area is static and the other is dynamic. the dynamic area allows scrolling of a region to take place. the areas cannot cross each other. only one scroll region is possible. 19.7.2 d isplay map the display map allows a flexible allocation of data in the memory to individual rows. sixteen words are provided in the display memory for this purpose. the lower 10 bits address the first word in the memory where the row data starts. this value is an offset in terms of 16-bit words from the start of display memory (8000h). the most significant bit enables the display when not within the scroll (dynamic) area. the display map memory is fixed at the first 16 words in the closed caption display memory. table 25 display map bit allocation bit function 11 text display enable, valid outside soft scroll area. 0 = disable; 1 = enable. 10 this bit is reserved, should be set to logic 0. 9 to 0 pointer to row data.
2000 feb 23 69 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.31 display map and data pointers. handbook, full pagewidth mbk966 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 10 11 3 4 9 10 11 12 13 14 15 display possible soft scrolling display possible display possible display map entries display data display memory text area row enable bit = 0
2000 feb 23 70 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.8 soft scroll action the dynamic scroll region is defined by the mmr scroll area, mmr scroll range, mmr top scroll line and the mmr status. the scroll area is enabled when the scon bit is set in mmr status. the position of the soft scroll area window is defined using the soft scroll position bits (ssp<3:0>) and the height of the window is defined using the soft scroll height bits (ssh<3:0>) both are in mmr scroll range. the rows that are scrolled through the window are defined using the start scroll row (sts<3:0>) and the stop scroll row (sps<3:0>) both are in mmr scroll area. the soft scrolling function is done by modifying the scroll line (scl<3:0>) in mmr top scroll line and the first scroll row value scr<3:0> in the mmr status. if the number of rows allocated to the scroll counter is larger than the defined visible scroll area, this allows parts of rows at the top and bottom to be displayed during the scroll function. the registers can be written throughout the field and the values are updated for display with the next field sync. care should be taken that the register pairs are written to by the software in the same field. only a region that contains only single height rows or only double height rows can be scrolled. txt: the display is organised as a fixed size of 25 rows (0 to 24) of 40 columns (0 to 39). this is the standard size for teletext transmissions. the control data in row 25 is not displayed but is used to configure the display page correctly. fig.32 soft scroll area. handbook, full pagewidth 15 mbk967 14 13 12 11 10 9 8 7 6 5 soft scroll position pointer ssp < 3:0 > e.g. 6 soft scroll height ssh < 3:0 > e.g. 4 soft scrolling area usable for osd display usable for osd display should not be used for osd display should not be used for osd display start scroll row sts < 3:0 > e.g. 3 start scroll row sps < 3:0 > e.g. 11 4 3 2 1 0 row
2000 feb 23 71 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.33 cc text areas. handbook, full pagewidth mbk977 row 0 row0 row1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 row2 row3 row4 row5 row6 row7 closed captioning data row n closed captioning data row n + 1 closed captioning data row n + 2 closed captioning data row n + 3 closed captioning data row n + 4 row8 row13 visible area for scrolling scroll area offset 0-63 lines row14 p01 nbc
2000 feb 23 72 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx fig.34 txt text area. handbook, full pagewidth 0 9 023 39 10 mbk968 control data non-displayable data byte 10 reserved row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
2000 feb 23 73 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.9 display positioning the display consists of the screen colour covering the whole screen and the text area that is placed within the visible screen area. the screen colour extends over a large vertical and horizontal range so that no offset is needed. the text area is offset in both directions relative to the vertical and horizontal sync pulses. fig.35 display area positioning. handbook, full pagewidth mgl150 56 m s text area start 0.25 character offset horizontal sync delay horizontal sync vertical sync 6 lines offset text vertical offset screen colour offset = 8 m s text area end screen colour area text area
2000 feb 23 74 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.9.1 s creen colour display area this area is covered by the screen colour. the screen colour display area starts with a fixed offset of 8 m s from the leading edge of the horizontal sync pulse in the horizontal direction. a vertical offset is not necessary. table 26 screen colour display area 19.9.2 t ext display area the text area can be defined to start with an offset in both the horizontal and vertical direction. table 27 text display area the horizontal offset is set in the mmr text area start. the offset is done in full width characters using tas<5:0> and quarter characters using hop<1:0> for fine setting. the values 00h to 08h for tas<5:0> will result in a corrupted display. the value 09h should also be avoided in the mmr text area start as corruption of the row 24 display can occur. alternative values are c8h or 49h to overcome this problem. the width of the text area is defined in the text area end register by setting the end character value tae<5:0>. this number determines where the background colour of the text area will end if set to extend to the end of the row. it will also terminate the character fetch process thus eliminating the necessity of a row end attribute. this entails however writing to all positions. the vertical offset is set in the text position vertical register. the offset value vol<5:0> is done in number of tv scan lines. note that the text position vertical register should not be set to 00h as the display busy interrupt is not generated in these circumstances. 19.10 character set to facilitate the global nature of the device the character set has the ability to accommodate a large number of characters, which can be stored in different matrices. position 525-line horizontal start at 8 m s after leading edge of horizontal sync for 56 m s. vertical line 9, field 1 (321, field 2) to leading edge of vertical sync (line numbering using 625 standard). position description horizontal up to 48 full sized characters per row. start position setting from 8 to 64 characters from the leading edge of horizontal sync. fine adjustment in quarter characters. vertical 256 lines (nominal 41 to 297). start position setting from leading edge of vertical sync, legal values are 4 to 64 lines (line numbering using 625 standard).
2000 feb 23 75 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.10.1 c haracter matrices the character matrices that can be accommodated in both display modes are: (h v planes) 12 9 1, 12 10 1, 12 13 1, 12 16 1. these modes allow two colours per character position. in cc mode two additional character matrices are available to allow four colours per character. (h v planes) 12 13 2, 12 16 2. the characters are stored physically in rom in a matrix of size either 12 10 or 12 16. 19.10.2 c haracter set selection four character sets are available in the device. a set can consist of alphanumeric characters as required by the wst or us closed captioning, customer definable on-screen display characters, and special graphic characters. cc: only a single character set can be used for display and this is selected using the basic set selection txt18.bs<1:0>. when selecting a character set in cc mode the twist set selection txt19.ts<1:0> should be set to the same value as txt18.bs<1:0> for correct operation. txt: two character sets can be displayed at once. these are the basic g0 set or the alternative g0 set (twist set). the basic set is selected using txt18.bs<1:0>. the alternative/twist character set is defined by txt19.ts<1:0>. since the alternative character set is an option it can be enabled or disabled using txt19.ten, and the language code that is defined for the alternative set is defined by txt19.tc<2:0>. the national option table is selected using txt18.not<3:0>. a maximum of 31 national option tables can be defined when combined with the east/ west control bit located in register txt4. an example of the character set selection and definitions is show in table 28. an example of the national option reference table is shown in table 29. only a certain number of national options will be relevant for each of the character sets. table 28 character set selection table 29 national option selection bs1/ts1 bs0/ts0 character set example language 0 0 set 0 latin 0 1 set 1 greek 1 0 set 2 cyrillic 1 1 set 3 french/arabic c12 c13 c14 not<3:0> = 0000 not<3:0> = 0001 not<3:0> = 0010 ... not<3:0> = 1110 0 0 0 english polish english ... polish 0 0 1 german german german ... german 0 1 0 swedish swedish swedish ... estonian 0 1 1 italian italian italian ... lettish 1 0 0 french french french ... russian 1 0 1 spanish - spanish ... serb-croat 1 1 0 czech czech turkish ... czech 111 --- ... -
2000 feb 23 76 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.11 rom addressing three roms are used to generate the correct pixel information. the first contains the national option look-up table, the second contains the basic character look-up table and the third contains the character pixel information. although these are individual roms, since they do not need to be accessed simultaneously they are all combined into a single rom unit. fig.36 rom organisation. handbook, full pagewidth mbk978 look-up set 3 0800h 0600h 0400h 0200h 0000h 0800h 2400h 0000h look-up set 2 character pixel data (71680 12-bit) look-up basic + national option 2048 locations @ 710 text or 430 text + 176 cc look-up set 1 look-up set 0
2000 feb 23 77 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.11.1 c haracter table cc: the character table is shown in fig.37. txt: one of the character set options (pan-european: latin) is shown in fig.30. fig.37 closed caption character table. handbook, full pagewidth mbk976 0 0 1 23 4 56 7 abcdef 89 sp 0 @ p ?p ? ! 1aq aq 1/2 " 2br br # 3cs cs $ 4 dt dt ? 5e ue u 1 2 3 4 5 6 7 8 9 a b c d e f ? 6f vf v 7g w g w ?( 8h xh x _ ) 9i yi y ?? : j zjz ? +; k [k? ? , < l ?l ? -= m ]m? ? . > n ?? /?o?on character code columns (bits 4 to 7) special characters in column 8 and 9 additional table locations for normal characters table locations for normal characters character code rows (bits 0 to 3)
2000 feb 23 78 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.12 rede?nable characters a number of dynamically redefinable characters (drc) are available. these are mapped onto the normal character codes, and replace the predefined rom value. there are 32 drcs, the first 16 occupy the character codes 80h to 8fh, the second 16 occupy the locations 90h to 9fh. this allows for 32 drcs or 16 special drcs. the remapping of the standard osd to the drcs is activated when the txt20.drcs enable bit is set. the selection of normal or special osd symbols is defined by the txt20.osd planes. each character is stored in a matrix of 12 16 1 (v h planes), this allows for all possible character matrices to be defined within a single location. fig.38 organisation of drc ram. handbook, full pagewidth mbk969 character 0 address (hex) character code character 0 address (hex) 80h 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f character 1 81h character 2 82h 8800 881f 8820 883f 8840 885f character 30 9eh character 31 12 bits 9fh 8bc0 8bdf 8be0 8bff a
2000 feb 23 79 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.12.1 d efining characters the drc ram is mapped into the 80c51 ram address space and starts at location 8800h. the character matrix is 12 bits wide and therefore requires two bytes to be written for each word, the first byte (even addresses), addresses the lower 8 bits and the lower nibble of the second byte (odd addresses) addresses the upper 4 bits. for characters of 9, 10 or 16 lines high the pixel information starts in the first address and continues sequentially for the required number of address. characters of 13 lines high are defined with an initial offset of 1 address, this is to allow for correct generation of fringing across boundaries of clustered characters see fig.39. the characters continue sequentially for 13 lines after which a further line can again be used for generation of correct fringing across boundaries of clustered characters. 19.13 display synchronization the horizontal and vertical synchronizing signals from the tv deflection are used as inputs. both signals can be inverted before being delivered to the phase selector section. cc: the polarity is controlled using either vpol or hpol bits in the mmr text position vertical. txt: the txt1.h polariy and txt1.v polarity bits control the polarity. a line locked 12 mhz clock is derived from the 12 mhz free running oscillator by the phase selector. this line locked clock is used to clock the whole of the display block. the horizontal and vertical sync signals are synchronized with the 12 mhz clock before being used in the display section. 19.14 video/data switch (fast blanking) polarity the polarity of the video/data (fast blanking) signal can be inverted. the polarity is set with the vdspol bit in the mmr rgb brightness. table 30 fast blanking signal polarity 19.15 video/data switch adjustment to take into account the delay between the rgb values and the vds signal due to external buffering, the vds signal can be moved in relation to the rgb signals. the vds signal can be set to be either a clock cycle before or after the rgb signal, or coincident with the rgb signal. this is done using vdel<2:0> in the mmr configuration. fig.39 13 line high drcs character format. handbook, halfpage line 13 from character above line 1 from character below top left pixel msb lsb mbk975 hex 440 003 00c 030 0c0 300 c00 c00 300 0c0 030 00c 003 000 1a8 000 line number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fringing top line bottom right pixel bottom line fringing line not used vdspol vds condition 0 1 rgb display 0 0 video display 1 0 rgb display 1 1 video display
2000 feb 23 80 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 19.16 rgb brightness control a brightness control is provided to allow the rgb upper output voltage level to be modified. the nominal value is 1 v into a 150 w resistor, but can be varied between 0.7 and 1.2 v. the brightness is set in rgb brightness register. table 31 rgb brightness 19.17 contrast reduction cc: this feature is not available in cc mode. txt : the cor bits in sfrs txt5 and txt6 control when the cor output of the device is activated (i.e. pulled low). this output is intended to act on the tvs display circuits to reduce contrast of the video when it is active. the result of contrast reduction is to improve the readability of the text in a mixed teletext and video display. the bits in the txt5 and txt6 sfrs allow the display to be set up so that, for example, the areas inside teletext boxes will be contrast reduced when a subtitle is being displayed but that the rest of the screen will be displayed as normal video. 20 memory mapped registers (mmr) the memory mapped registers are used to control the display. the registers are mapped into the microcontroller movx address space, starting at address 87f0h and extending to 87ffh. table 32 mmr address summary bri3 to bri0 rgb brightness 0000 lowest value ... ... 1111 highest value register number memory address function 0 87f0h display control 1 87f1h text position vertical 2 87f2h text area start 3 87f3h fringing control 4 87f4h text area end 5 87f5h scroll area 6 87f6h scroll range 7 87f7h rgb brightness 8 87f8h status 9 87f9h reserved 10 87fah reserved 11 87fbh reserved 12 87fch hsync delay 13 87fdh vsync delay 14 87feh top scroll line 15 87ffh con?guration
2000 feb 23 81 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx table 33 mmr map add r/w name 7 6 5 4 3 2 1 0 reset 87f0 r/w display control src3 src2 src1 src0 - msh mod1 mod0 00h 87f1 r/w text position vertical vpol hpol vol5 vol4 vol3 vol2 vol1 vol0 00h 87f2 r/w text area start hop1 hop0 tas5 tas4 tas3 tas2 tas1 tas0 00h 87f3 r/w fringing control frc3 frc2 frc1 frc0 frdn frde frds frdw 00h 87f4 r/w text area end -- tae5 tae4 tae3 tae2 tae1 tae0 00h 87f5 r/w scroll area ssh3 ssh2 ssh1 ssh0 ssp3 ssp2 ssp1 ssp0 00h 87f6 r/w scroll range sps3 sps2 sps1 sps0 sts3 sts2 sts1 sts0 00h 87f7 r/w rgb brightness vdspol --- bri3 bri2 bri1 bri0 00h 87f8 r status busy field scon flr scr3 scr2 scr1 scr0 00h w -- scon flr scr3 scr2 scr1 scr0 00h 87fc r/w hsync delay - hsd6 hsd5 hsd4 hsd3 hsd3 hsd1 hsd0 00h 87fd r/w vsync delay - vsd6 vsd5 vsd4 vsd3 vsd2 vsd1 vsd0 00h 87fe r/w top scroll line ---- scl3 scl2 scl1 scl0 00h 87ff r/w con?guration cc vdel2 vdel1 vdel0 txt/v -- - 00h
2000 feb 23 82 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx table 34 mmr bit de?nition register function display control src3 to src0 screen colour de?nition msh meshing all background colours (logic 1) mod2 to mod0 00 = video 01 = full text 10 = mixed screen colour 11 = mixed video text position vertical vpol inverted input polarity (logic 1) hpol inverted input polarity (logic 1) vol5 to vol0 display start vertical offset from vsync (lines) text area start hop1 to hop0 ?ne horizontal offset in quarter of characters tas5 to tas0 text area start fringing control frc3 to frc0 fringing colour, value address of clut frdn fringe in north direction (logic 1) frde fringe in east direction (logic 1) frds fringe in south direction (logic 1) frdw fringe in west direction (logic 1) text area end tae5 to tae0 text area end, in full characters scroll area ssh3 to ssh0 soft scroll height ssp3 to ssp0 soft scroll position scroll range sps3 to sps0 stop scroll row sts3 to sts0 start scroll row rgb brightness vdspol vds polarity 0 = rgb (1), video (0) 1 = rgb (0), video (1) bri3 to bri0 rgb brightness control
2000 feb 23 83 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx status read busy access to display memory could cause display problems (logic 1) field even ?eld (logic 1) flr active ?ash region background only displayed (logic 1) scr3 to scr0 ?rst scroll row status write scon scroll area enabled (logic 1) flr active ?ash region background colour only displayed (logic 1) scr3 to scr0 ?rst scroll row hsync delay hsd6 to hsd0 hsync delay, in full size characters vsync delay vsd6 to vsd0 vsync delay in number of 8-bit 12 mhz clock cycles top scroll line scl3 to scl0 top line for scroll con?guration cc closed caption mode (logic 1) vdel2 to vdel0 pixel delay between vds and rgb output 000 = vds switched to video, not active 001 = vds active one pixel earlier then rgb 010 = vds synchronous to rgb 100 = vds active one pixel after rgb txt/v busy signal switch horizontal (logic 1) register function
2000 feb 23 84 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 21 limiting values in accordance with absolute maximum rating system (iec 60134). note 1. this maximum value refers to 5 v tolerant i/os and may be 6 v maximum but only when v dd is present. 22 characteristics v dd = 3.3 v 10%; v ss =0v; t amb = - 20 to +70 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit v ddx supply voltage (all supplies) - 0.5 +4.0 v v i input voltage (any input) note 1 - 0.5 v dd + 0.5 or 4.1 v v o output voltage (any output) note 1 - 0.5 v dd + 0.5 v i o output current (each output) - 10 ma i iok dc input or output diode current - 20 ma t amb ambient temperature - 20 +70 c t stg storage temperature - 55 +125 c symbol parameter conditions min. typ. max. unit supplies v ddx any supply voltage (v dd to v ss ) 3.0 3.3 3.6 v i ddp periphery supply current note 1 1 -- ma i ddc core supply current - 15 18 ma i ddc(id) idle mode core supply current - 4.6 6 ma i ddc(pd) power-down mode core supply current - 0.76 1 ma i ddc(stb) standby mode core supply current - 5.1 9 ma i dda analog supply current - 45 48 ma i dda(id) idle mode analog supply current - 0.87 1 ma i dda(pd) power-down mode analog supply current - 0.45 0.7 ma i dda(stb) standby mode analog supply current - 809 950 m a digital inputs reset v il low-level input voltage -- 1.00 v v ih high-level input voltage 1.85 -- v v hys hysteresis voltage of schmitt trigger input 0.44 - 0.58 v i li input leakage current v i =0 -- 0.17 m a r pd equivalent pull-down resistance v i =v dd 55.73 70.71 92.45 k w
2000 feb 23 85 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx hsync, vsync v il low-level input voltage -- 0.96 v v ih high-level input voltage 1.80 -- v v hys hysteresis of schmitt trigger input 0.40 - 0.56 v i li input leakage current v i =0tov dd -- 0.00 m a digital outputs frame, vds v ol low-level output voltage i ol =3ma -- 0.13 v v oh high-level output voltage i oh = 3 ma 2.84 -- v t r output rise time 10% to 90%; c l =70pf 7.50 8.85 10.90 ns t f output fall time 10% to 90%; c l =70pf 6.70 7.97 10.00 ns cor ( open - drain output ) v ol low-level output voltage i ol =3ma -- 0.14 v v oh high-level pull-up output voltage i ol = - 3 ma; push-pull 2.84 -- v v il low-level input voltage -- 0.00 v v ih high-level input voltage 0.00 - 5.50 v i li input leakage current v i = 0 to v dd -- 0.12 m a t r output rise time 10% to 90%; c l =70pf 7.20 8.64 11.10 ns t f output fall time 10% to 90%; c l =70pf 4.90 7.34 9.40 ns digital input/outputs p0.0 to p0.4, p0.7, p1.0 to p1.1, p2.1 to p2.7, p3.0 to p3.7 v il low-level input voltage -- 0.98 v v ih high-level input voltage 1.78 -- v v hys hysteresis of schmitt trigger input 0.41 - 0.55 v i li input leakage current v i =0tov dd -- 0.01 m a v ol low-level output voltage i ol =4ma -- 0.18 v v oh high-level output voltage i oh = - 4ma push-pull 2.81 - 5.50 v t r output rise time 10% to 90%; c l =70pf push-pull 6.50 8.47 10.70 ns t f output fall time 10% to 90%; c l =70pf 5.70 7.56 10.00 ns symbol parameter conditions min. typ. max. unit
2000 feb 23 86 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx p1.2, p1.3 and p2.0 v il low-level input voltage -- 0.99 v v ih high-level input voltage 1.80 -- v v hys hysteresis voltage of schmitt trigger input 0.42 - 0.56 v i li input leakage current v i =0tov dd -- 0.02 m a v ol low-level output voltage i ol =4ma -- 0.17 v v oh high-level output voltage i oh = - 4ma push-pull 2.81 - 5.50 v t r output rise time 10% to 90%; c l =70pf push-pull 7.00 8.47 10.50 ns t f output fall time 10% to 90%; c l =70pf 5.40 7.36 9.30 ns p0.5 and p0.6 v il low-level input voltage -- 0.98 v v ih high-level input voltage 1.82 -- v i li input leakage current v i =0tov dd -- 0.11 m a v hys hysteresis voltage of schmitt trigger input 0.42 - 0.58 v v ol low-level output voltage i ol =8ma -- 0.20 v v oh high-level output voltage i oh = - 8ma push-pull 2.76 - 5.50 v t r output rise time 10% to 90%; c l =70pf push-pull 7.40 8.22 8.80 ns t f output fall time 10% to 90%; c l =70pf 4.20 4.57 5.20 ns p1.4 to p1.7 ( open - drain ) v il low-level input voltage -- 1.08 v v ih high-level input voltage 1.99 -- v v hys hysteresis voltage of schmitt trigger input 0.49 - 0.60 v i li input leakage current v i =0tov dd -- 0.13 m a v ol low-level output voltage i ol =8ma -- 0.35 v t f output fall time 10% to 90%; c l =70pf 69.70 83.67 103.30 ns symbol parameter conditions min. typ. max. unit
2000 feb 23 87 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx analog inputs cvbs0 and cvbs1 v sync sync voltage amplitude 0.1 0.3 0.6 v v vid(p-p) video input voltage amplitude (peak-to-peak value) 0.7 1.0 1.4 v z source source impedance 0 - 250 w v ih high-level input voltage 3.0 - v dda + 0.3 v c i input capacitance -- 10 pf iref r gnd resistor to ground resistor tolerance 2% - 24 - k w adc0 to adc3 v ih high-level input voltage -- v dda v c i input capacitance -- 10 pf vpe v ih high-level input voltage -- 9.0 v analog outputs r, g and b i ol output current (black level) v dda = 3.3 v - 10 - +10 m a i oh output current (maximum intensity) v dda = 3.3 v intensity level code = 31 dec 6.0 6.67 7.3 ma output current (70% of full intensity) v dda = 3.3 v intensity level code = 0 dec 4.2 4.7 5.1 ma r load load resistor to v ssa resistor tolerance 5% - 150 -w c l load capacitance -- 15 pf analog input/output sync_filter c sync storage capacitor to ground - 100 - nf v sync sync ?lter level voltage for nominal sync amplitude 0.35 0.55 0.75 v crystal oscillator xtalin v il low-level input voltage v ssa -- v v ih high-level input voltage -- v dda v c i input capacitance -- 10 pf symbol parameter conditions min. typ. max. unit
2000 feb 23 88 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx notes 1. peripheral current is dependent on external components and voltage levels on i/os. 2. crystal order number 4322 143 05561. 3. if the 4322 143 05561 crystal is not used, then the formulae in the crystal specification should be used. where c io = 7 pf, the mean of the capacitances due to the chip at xtalin and at xtalout. c ext is a value for the mean of the stray capacitances due to the external circuit at xtalin and xtalout. the maximum value for the crystal holder capacitance is to ensure start-up, c osc may need to be reduced from the initially selected value. 4. c osc(typ) =2c l - c io - c ext 5. c 0(max) =35 - 1 2 (c osc +c io +c ext ) xtalout c o output capacitance -- 10 pf crystal speci?cation; notes 2 and 3 f xtal nominal frequency fundamental mode - 12 - mhz c l crystal load capacitance - -30pf c 1 crystal motional capacitance t amb =25 c -- 20 ff r r resonance resistance t amb =25 c -- 60 w c osc capacitors at xtalin, xtalout t amb =25 c - note 4 - pf c 0 crystal holder capacitance t amb =25 c -- note 5 pf t xtal temperature range - 20 +25 +85 c x j adjustment tolerance t amb =25 c -- 50 10 - 6 x d drift -- 100 10 - 6 symbol parameter conditions min. typ. max. unit
2000 feb 23 89 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx table 35 i 2 c-bus characteristics notes 1. a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v il(min) of the scl signal) in order to bridge the undefined region of the falling edge of scl. 2. the maximum f hd;dat has only to be met if the device does not stretch the low period t low of the scl signal. 3. a fast-mode i 2 c-bus device can be used in a standard mode i 2 c-bus system but the requirement t su;dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r(max) +t su;dat = 1000 + 250 +1250 ns (according to the standard mode i 2 c-bus specification) before the scl line is released. 4. c b = total capacitance of one bus line in pf. symbol parameter fast-mode i 2 c-bus unit min. max. f scl scl clock frequency 0 400 khz t buf bus free time between a stop and start condition 1.3 -m s t hd;sta hold time (repeated) start condition. after this period, the ?rst clock pulse is generated. 0.6 -m s t low low period of the scl clock 1.3 -m s t high high period of the scl clock 0.6 -m s t su;sta set-up time for a repeated start condition 0.6 -m s t hd;dat data hold time; notes 1 and 2 0 0.9 m s t su;dat data set-up time, note 3 100 - ns t r rise time of both sda and scl signals; note 4 20 300 ns t f fall time of both sda and scl signals; note 4 20 300 ns t su;sto set-up time for stop condition 0.6 -m s c b capacitive load for each bus line - 400 pf
2000 feb 23 90 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 23 quality and reliability this device will meet philips semiconductors general quality specification for business group consumer integrated circuits snw-fq-611-part e . the principal requirements are shown in tables 36 to 39. 23.1 group a table 36 acceptance tests per lot 23.2 group b table 37 processability tests (by package family) 23.3 group c table 38 reliability tests (by process family) table 39 reliability tests (by device type) notes to tables 36 to 39 1. ppm = fraction of defective devices, in parts per million. 2. fpm = fraction of devices failing at test condition, in failures per million. test requirements mechanical cumulative target: <80 ppm electrical cumulative target: <100 ppm test requirements solderability 0/16 on all lots mechanical 0/15 on all lots solder heat resistance 0/15 on all lots test conditions requirements operational life 168 hours at t j = 150 c <1000 fpm at t j = 150 c humidity life temperature, humidity, bias 1000 hours, 85 c, 85% rh (or equivalent test) <2000 fpm temperature cycling performance t stg(min) to t stg(max) <2000 fpm test conditions requirements esd and latch-up esd human body model 100 pf, 1.5 k w 2000 v esd machine model 200 pf, 0 w 200 v latch-up 100 ma, 1.5 v dd (absolute maximum)
2000 feb 23 91 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 24 application information o k, full pagewidth mbk980 2 v dd v dd v afc av status program + program - plus( + ) minus( - ) menu v tune v ss v ss v ss v dd v dd v dd v dd v ssc v ddp v ddc v ssp v ssa v ss vpe v ss v ss v ss p2.1/pwm0 3 p2.2/pwm1 4 p2.3/pwm2 5 p2.4/pwm3 6 p2.5/pwm4 7 p2.6/pwm5 8 p2.7/pwm6 9 p3.0/adc0 p3.1/adc1 p3.2/adc2 p0.0 vhf-l vhf-h uhf tv control signals p3.3/adc3 10 11 12 13 14 15 16 17 18 19 20 21 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 g b v dda hsync vds r vsync xtalout xtalin oscgnd p1.0/int1 reset p3.4/pwm7 iref 100 nf 100 nf 100 nf frame sync_filter cvbs1 cvbs0 cvbs (if) cvbs (scart) 22 23 24 26 25 29 27 28 1 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 52 p2.0/tpwm a2 p1.4/scl1 p1.7/sda0 p1.6/scl0 p1.3/t1 p1.2/int0 p1.1/t0 p1.5/sda1 sda a1 scl a0 rc brightness contrast saturation hue volume (l) volume (r) v dd v ss 1 k w 1 k w 150 w 24 k w v dd 40 v v ss v ss v dd v ss ph2369 47 m f v dd v ss 100 nf cor v ss v dd 47 m f 10 m f 100 nf 56 pf v dd v dd v dd v ss v ss eeprom pcf8582e saa55xx ir receiver 12 mhz to tv's display circuits tv control signals field flyback line flyback fig.40 application diagram.
2000 feb 23 92 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 25 emc guidelines optimization of circuit return paths and minimisation of common mode emission will be assisted by using a double sided printed-circuit board (pcb) with low inductance ground plane. on a single sided pcb local ground plane under the whole ic should be present as shown in fig.41. this should be connected by the widest possible connection back to the pcb ground connection, and bulk electrolytic decoupling capacitor. it should preferably not connect to other grounds on the way and no wire links should be present in this connect. the use of wire links increases ground bounce by introducing inductance into the ground. the supply pins can be decoupled at the pin to the ground plane under the ic. this is easily accomplished using surface mount capacitors, which are more effective than leaded components at high frequency. using a device socket will unfortunately add to the area and inductance of the external bypass loop. a ferrite bead or inductor with resistive characteristics at high frequencies may be utilised in the supply line close to the decoupling capacitor to provide a high-impedance. to prevent pollution by conduction onto the signal lines (which may then radiate) signals connected to the v dd supply via a pull-up resistor should not be connected to the ic side of this ferrite component. oscgnd should be connected only to the crystal load capacitors and not the local or circuit gnd. physical connection distances to associated active devices should be short. output traces should be routed with close proximity to mutually coupled ground return paths. fig.41 power supply connections for emc. handbook, full pagewidth electrolytic decoupling capacitor (2 m f) ferrite beads sm decoupling capacitors (10 to 100 nf) under-ic gnd plane ic mbk979 v ssc v ssa v ddp v ssp v ddc v dda gnd + 3.3 v other gnd connections under-ic gnd plane gnd connection note: no wire links
2000 feb 23 93 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 26 references 1. 80c51 based 8-bit microcontrollers. philips semiconductors (ref. ic20). 2. the i 2 c-bus and how to use it (including specification). philips semiconductors. 3. enhanced teletext specification european telecommunication standard ets 300 706. 4. world system teletext and data broadcasting system. dti. december 1987 (525 wst only). 5. specification of the domestic video programme delivery control system (pdc); ebu tech. 3262-e. 6. recommended practise for line 21 data service eia-608.
2000 feb 23 94 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 27 package outlines unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot247-1 95-03-11 99-12-27 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 47.9 47.1 14.0 13.7 3.2 2.8 0.18 1.778 15.24 15.80 15.24 17.15 15.90 1.73 5.08 0.51 4.0 ms-020 m h c (e ) 1 m e a l seating plane a 1 w m b 1 d a 2 z 52 1 27 26 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z e a max. 12 a min. a max. sdip52: plastic shrink dual in-line package; 52 leads (600 mil) sot247-1
2000 feb 23 95 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.08 0.08 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 136e20 ms-026 00-01-19 00-02-01 d (1) (1) (1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e q e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1
2000 feb 23 96 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 28 soldering 28.1 introduction to soldering through-hole mount packages this text gives a brief insight to wave, dip and manual soldering. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). wave soldering is the preferred method for mounting of through-hole mount ic packages on a printed-circuit board. 28.2 soldering by dipping or by solder wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joints for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg(max) ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 28.3 manual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. 28.4 suitability of through-hole mount ic packages for dipping and wave soldering methods note 1. for sdip packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. package soldering method dipping wave dbs, dip, hdip, sdip, sil suitable suitable (1)
2000 feb 23 97 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx 29 definitions 30 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 31 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2000 feb 23 98 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx notes
2000 feb 23 99 philips semiconductors preliminary speci?cation enhanced tv microcontrollers with on-screen display (osd) saa55xx notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2000 69 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 753504/02/pp 100 date of release: 2000 feb 23 document order number: 9397 750 06787

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